33.3.2.1.1 One-Wire Enable

The UPDI pin has a constant pull-up when enabled, and by driving the UPDI line low for more than 200 ns, a connected programmer/debugger will initiate the start-up sequence. As a prerequisite, the UPDI pin must be configured in UPDI function mode, either by setting the UPDIPINCFG bit in SYSCFG0 fuse to ‘1’ or by applying an HV pulse on the RESET pin, thus overriding the configuration of UPDIPINCFG.

Follow this sequence to enable the UPDI:
  1. Drive the UPDI pin low for more than 200 ns, and release it.
    The UPDI pin has an internal pull-up resistor, and by driving the UPDI pin low for more than 200 ns, a connected programmer will initiate the start-up sequence:
    • An edge detector starts driving the UPDI pin low, so when the programmer releases the line, it will stay low
    • The UPDI clock is started. The UPDI will continue to drive the line low until the clock is stable and ready for the UPDI to use

      The expected arrival time for the clock will depend on the oscillator implementation regarding the accuracy, overshoot, and readout of the oscillator calibration

    • The data line will be released by the UPDI and pulled high when the oscillator is ready and stable
  2. Poll the UPDI pin to detect when the pin transitions to high again.

    This transition indicates that the edge detector has released the pin (pull-up), and the UPDI can receive a SYNCH character.

  3. Send a SYNCH character 0x55.

    After a successful SYNCH character transmission, the first instruction frame can be transmitted.

  4. Send the NVMPROG key using the KEY instruction.

    Sending this key clears the lock bits, and the Programming Start (PROGSTART) bit in the ASI_SYS_STATUS is set. The device is now prepared for programming.

  5. After the programming is finished, reset the UPDI by writing the UPDI Disable (UPDIDIS) bit in the Control B (UPDI.CTRLB) register to ‘1’ using the STCS instruction.

    Disabling the UPDI and hence, the accompanying clock request, will reduce power consumption.

The timing of the enable sequence is shown in Figure 33-5, where the active driving periods for the programmer and edge detector are included. The ‘UPDI pin’ waveform shows the pin value at any given time.

Figure 33-5. UPDI Enable Sequence

The delay given for the edge detector active drive period is a typical start-up time waiting for 256 cycles on a 32 MHz oscillator + the calibration readout. Refer to the Electrical Characteristics section for details on the expected start-up times.

Note: The first instruction issued after the initial enable SYNCH does not need an extra SYNCH to be sent because the enable sequence SYNCH sets up the Baud Rate Generator for the first instruction.

When the debugger detects that the line is high, the initial SYNCH character 0x55 must be transmitted to synchronize the UPDI communication data rate. If the Start bit of the SYNCH character is not sent within maximum TDebZ, the UPDI will disable itself, and the UPDI enabling sequence must be reinitiated. If the timing is violated, the UPDI is disabled to avoid unintentional enabling of the UPDI. See Disable During Start-Up for more details.

Note: The actual values for TRES, TUPDI, TDeb0, and TDebZ can be found in the Electrical Characteristics section.