11.4.2 Natural Order (Hardware) Priority

When vectored interrupts are enabled and more than one interrupt with the same user specified priority level is requested, the priority conflict is resolved by using a method called “Natural Order Priority”. Natural order priority is a fixed priority scheme that is based on the IVT.

Table 11-2. Interrupt Vector Priority Table
Vector

Number

Interrupt

source

Vector

Number

(cont.)

Interrupt

source

(cont.)

0x0Software Interrupt0x2B-
0x1HLVD (High/Low-Voltage Detect)0x2CCM2 (Comparator)
0x2OSF (Oscillator Fail)0x2DCLC2
0x3CSW (Clock Switching)0x2EPWM2RINT
0x4NVM0x2FPWM2GINT
0x5CLC1 (Configurable Logic Cell)0x30INT1
0x6CRC (Cyclic Redundancy Check)0x31CLC7
0x7IOC (Interrupt-On-Change)0x32CWG1 (Complementary Waveform Generator)
0x8INT00x33NCO1 (Numerically Controlled Oscillator)
0x9ADCH1 (ADC Context 1)0x34DMA2SCNT
0xAAD (ADC Conversion Complete)0x35DMA2DCNT
0xBACT (Active Clock Tuning)0x36DMA2OR
0xCCM1 (Comparator)0x37DMA2A
0xDADCH2 (ADC Context 2)0x38I2C1RX
0xEADCH3 (ADC Context 3)0x39I2C1TX
0xFADCH4 (ADC Context 4)0x3AI2C1
0x10ZCD (Zero-Cross Detection)0x3BI2C1E
0x11CLC50x3C-
0x12IOCSR (Interrupt-On-Change Signal Routing Ports)0x3DCLC3
0x13-0x3EPWM3RINT
0x14DMA1SCNT (Direct Memory Access)0x3FPWM3GINT
0x15DMA1DCNT0x40U2RX
0x16DMA1OR0x41U2TX
0x17DMA1A0x42U2E
0x18SPI1RX (Serial Peripheral Interface)0x43U2
0x19SPI1TX0x44-
0x1ASPI10x45CLC4
0x1BTMR20x46CCP2 (Capture/Compare/PWM)
0x1CTMR10x47SCAN
0x1DTMR1G0x48 - 0x4B-
0x1ECCP1 (Capture/Compare/PWM)0x4CDMA3SCNT
0x1FTMR00x4DDMA3DCNT
0x20U1RX0x4EDMA3OR
0x21U1TX0x4FDMA3A
0x22U1E0x50INT2
0x23U10x51CLC8
0x24TMR30x52TU16B (Universal Timer 16B)
0x25TMR3G0x53TMR4
0x26PWM1RINT0x54DMA4SCNT
0x27PWM1GINT0x55DMA4DCNT
0x28-0x56DMA4OR
0x29CLC60x57DMA4A
0x2ATU16A (Universal Timer 16A) 0x58-

The natural order priority scheme goes from high-to-low with increasing vector numbers, with 0 being the highest priority and decreasing from there.

For example, when two concurrently occurring interrupt sources that are both designated high priority, using the IPRx register will be resolved using the natural order priority (i.e., the interrupt with a lower corresponding vector number will preempt the interrupt with the higher vector number).

The ability for the user to assign every interrupt source to high- or low-priority levels means that the user program can give an interrupt with a low natural priority, a higher overall priority level.