24.8.4 CLCnSEL0

Generic CLCn Data 1 Select Register
Name: CLCnSEL0
Address: 0x0D8

Bit 76543210 
   D1S[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset xxxxxx 

Bits 5:0 – D1S[5:0] CLCn Data1 Input Selection

Table 24-2. CLC Input Selection
DyS Input SourceDyS (cont.)Input Source (cont.)DyS (cont.)Input Source (cont.)
[0] 0000 0000CLCIN0PPS[20] 0001 0100TMR2[40] 0010 1000CLC4
[1] 0000 0001CLCIN1PPS[21] 0001 0101TMR3[41] 0010 1001CLC5
[2] 0000 0010CLCIN2PPS[22] 0001 0110TMR4[42] 0010 1010CLC6
[3] 0000 0011CLCIN3PPS[23] 0001 0111CCP1[43] 0010 1011CLC7
[4] 0000 0100CLCIN4PPS[24] 0001 1000CCP2[44] 0010 1100CLC8
[5] 0000 0101CLCIN5PPS[25] 0001 1001PWM1S1P1_OUT[45] 0010 1101U1TX
[6] 0000 0110CLCIN6PPS[26] 0001 1010PWM1S1P2_OUT[46] 0010 1110U2TX
[7] 0000 0111CLCIN7PPS[27] 0001 1011PWM2S1P1_OUT[47] 0010 1111SPI1_SDO
[8] 0000 1000FOSC[28] 0001 1100PWM2S1P2_OUT[48] 0011 0000SPI1_SCK
[9] 0000 1001HFINTOSC(1)[29] 0001 1101PWM3S1P1_OUT[49] 0011 0001SPI1_SS
[10] 0000 1010LFINTOSC(1)[30] 0001 1110PWM3S1P2_OUT[50] 0011 0010I2C_SCL
[11] 0000 1011MFINTOSC(1)[31] 0001 1111NCO1[51] 0011 0011I2C_SDA
[12] 0000 1100MFINTOSC (31.25 kHz)(1)[32] 0010 0000CMP1_OUT[52] 0011 0100CWG1A
[13] 0000 1101SFINTOSC (1 MHz)(1)[33] 0010 0001CMP2_OUT[53] 0011 0101CWG1B
[14] 0000 1110SOSC(1)[34] 0010 0010ZCD[54] 0011 0110TU16A
[15] 0000 1111EXTOSC(1)[35] 0010 0011IOC[55] 0011 0111TU16B
[16] 0001 0000ADCRC(1)[36] 0010 0100HLVD_OUT ...—
[17] 0001 0001CLKR[37] 0010 0101CLC1...—
[18] 0001 0010TMR0[38] 0010 0110CLC2...—
[19] 0001 0011TMR1[39] 0010 0111CLC3[63] 0011 1111—
Note:
  1. Requests clock.
Reset States: 
POR/BOR = xxxxxx
All Other Resets = uuuuuu