4.2 PWM Generation
The Timer/Counter Type D (TCD) peripheral is used to generate the PWM signals that control half-bridge driver inputs.
The timer is configured in One Ramp mode, and its functionality is presented in Figure 4-3.
In One Ramp mode, the TCD cycle period is:
For example, using an input clock of 24 MHz, a prescaler of 1:1, and a CMPBCLR value of 512, will give a period of 21.375 µs, or a frequency of approximately 46.783 kHz.
The dead time is set in software during external changes on the timer’s duty cycle.
For this application, the operation region is above 50% duty cycle to operate in quadrant one and two.
PWM Signal Routing
For six steps trapezoidal control, three half-bridge drivers must be controlled by a microcontroller. The TCD has only four waveform outputs that allow direct control of only two half-bridge drivers. The other two phases are created with the help of Custom Configurable Logic (CCL).
The WOC and WOD outputs of the TCD peripheral are available to the physical pins on the microcontroller and they are used to drive phase C.
The WOA and WOB outputs of the TCD peripheral are used to control the other two phases. With the help of CCL logic, the WOA and WOB signals are available on two different pairs of pins.
The equivalent logic for one phase, based on the behavior of the system, is configured through the TRUTH registers:
The CCL logic implements smart routing of PWM signals to the half-bridge drivers, allowing control of two motor phases using only one complimentary PWM pair (WOA and WOB), as described in the use cases below.
If the characteristic state of the phase is LOW, WOA is routed to the low-side transistor, while the WOB will be routed to the high-side transistor.
If the characteristic state of the phase is HIGH, the WOA is routed to the high-side transistor and the WOB to the low-side transistor.