16.14.1 PORTx
Important:
- Writes to PORTx are actually written to the corresponding LATx register. Reads from PORTx register return actual I/O pin values.
- The PORT bit associated with the
MCLR pin is read-only and will read
‘
1
’ when the MCLR function is enabled (LVP =1
or (LVP =0
and MCLRE =1
)) - Refer to the “Pin Allocation Table” for details about MCLR pin and pin availability per port
- Unimplemented bits will read back
as ‘
0
’ - Bits RB6 and RB7 read
‘1’
while in Debug mode
Name: | PORTx |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Rx7 | Rx6 | Rx5 | Rx4 | Rx3 | Rx2 | Rx1 | Rx0 | ||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | x | x | x | x | x | x | x | x |
Bits 0, 1, 2, 3, 4, 5, 6, 7 – Rxn Port I/O Value
Reset States: |
|
Value | Description |
---|---|
1 |
PORT pin is ≥ VIH |
0 |
PORT pin is ≤ VIL |