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PIC16F18126/46 Full-Featured 14/20-Pin Microcontrollers

PIC16F18126 PIC16F18146

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32 EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
32.6 Register Definitions: EUSART Control
32.6.4 RCxREG
RCxREG

Introduction
PIC16F181 Family Summary
Core Features
1 Packages
2 Pin Diagrams
3 Pin Allocation Tables
4 Guidelines for Getting Started with PIC16F181 Microcontrollers
5 Register and Bit Naming Conventions
6 Register Legend
7 Enhanced Mid-Range CPU
8 Device Configuration
9 Memory Organization
10 Resets
11 OSC - Oscillator Module (With Fail-Safe Clock Monitor)
12 INT - Interrupts
13 Power-Saving Modes
14 WWDT - Windowed Watchdog Timer
15 NVM - Nonvolatile Memory Control
16 I/O Ports
17 IOC - Interrupt-on-Change
18 PPS - Peripheral Pin Select Module
19 CRC - Cyclic Redundancy Check Module with Memory Scanner
20 PMD - Peripheral Module Disable
21 CLKREF - Reference Clock Output Module
22 TMR0 - Timer0 Module
23 TMR1 - Timer1 Module with Gate Control
24 TMR2 - Timer2 Module
25 NCO - Numerically Controlled Oscillator Module
26 CWG - Complementary Waveform Generator Module
27 CCP - Capture/Compare/PWM Module
28 Capture, Compare, and PWM Timers Selection
29 PWM - Pulse-Width Modulator with Compare
30 CLC - Configurable Logic Cell
31 MSSP - Host Synchronous Serial Port Module
32 EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
33 ADC - Analog-to-Digital Converter with Computation Module
34 DAC - Digital-to-Analog Converter Module
35 CMP - Comparator Module
36 FVR - Fixed Voltage Reference
37 Temperature Indicator Module
38 ZCD - Zero-Cross Detection Module
39 Charge Pump
40 Instruction Set Summary
41 ICSP™ - In-Circuit Serial Programming™
42 Register Summary
43 Electrical Specifications
44 DC and AC Characteristics Graphs and Tables
45 Packaging Information
46 Appendix A: Revision History
Microchip Information

32.6.4 RCxREG

Receive Data Register

Name:	RCxREG
Offset:	0x070C,0x0716


Bit	7	6	5	4	3	2	1	0
	RCREG[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – RCREG[7:0] Receive data

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Bits 7:0 – RCREG[7:0] Receive data

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