2 Overview

The SPI bus is a synchronous serial communication interface based on four types of logic signals:

  • SCK: Serial Clock (output from the host)
  • MOSI: Host Output Client Input (data output from the host)
  • MISO: Host Input Client Output (data output from the client)
  • SS: Client Select (active-low, data output from the host)

This peripheral is used for short distance and high-speed communication, primarily in embedded systems. The SPI devices communicate in Full-Duplex mode, using a channel for transmitting and one for receiving data. The SPI is based on a host-client architecture with a single host at a time and one or more clients. The host device is the only one that can generate a clock, thus it is the initiator of the data exchange. The SPI host device uses the same SCK, MOSI and MISO channels for all the clients, but usually individual lines of SS for each of the clients. The host device selects the desired client by pulling the SS signal low.

The data to be sent will be stored in either a data register or, if a transmission is already in progress and the Buffer mode was activated, in a buffer register. The data are sent out serially on the MOSI channel, using a shift register, and every bit is synchronized using the SPI clock generator. While every bit is shifted out, new data are received on the MISO channel from the client and are shifted in a receiver buffer and further in the receive DATA register. If the receiver is busy, meaning there are already data in the receive DATA register and the Buffer mode was activated, the data will be temporarily stored in a second receiver buffer. The Buffer mode is activated by setting high the BUFEN bit of the CTRLB register.

Figure 2-1. SPI Block Diagram

The SPI module has five registers. One register is used for data transfer and storage, two registers are used for Interrupt flags, and the last two registers (CTRLA and CTRLB) are for initializations. All the configurations required to make the peripheral work correctly are reduced to changing some bits in the CTRLA register, while the CTRLB register is focused on different modes of operation that are optional. More details regarding the registers can be found in the family data sheet of the device, on the register summary of the peripheral section.

Figure 2-2. Register Summary - SPIn