38.1 Rev. A - 04/2021

• Initial document release

• ATtiny804/1604 Data Sheet
• ATtiny806/1606 Data Sheet
• ATtiny807/1607 Data Sheet

• ATtiny804/806/807/1604/1606/1607 Data Sheet (this document)

The following items are referring to changes between the latest revisions of the obsolete documents and this document:

• Updated the document to Microchip editing standard
• Updated terminology used throughout data sheet:
  • Master is replaced by host
  • Slave is replaced by client
• Removed related links
• Removed the Acronyms and Abbreviations section
• Removed the content of the Instruction Set Summary section. This section now refers to the external Instruction Set Manual instead.
• Removed device-specific information from peripheral sections
• Restructured sections related to system dependencies within the peripheral sections

• Device-specific information is restructured/changed to comply with the devices documented in this document
  • Features
  • Pinout
  • I/O Multiplexing and Considerations
  • Ordering Information
  • Package Drawings
• Block diagram updated
• Pinout diagrams updated:
  • 14-Pin SOIC
  • 20-Pin SOIC
  • 20-Pin VQFN
  • 24-Pin VQFN
• Memories
  • Updated Fuse Description section with factory-programmed default values
• Peripherals and Architecture
  • Updated Peripheral Address Match table
  • Updated Interrupt Vector Mapping table
• Package Drawings
  • Updated the Drawing Numbers table
  • Removed MSL numbers
  • Thermal Considerations section moved inside the Package Drawings section

• Updated Features section
• Removed duplicate information after the AVR CPU architecture figure
• Emphasized that the Arithmetic Logic Unit (ALU) is doing its operations against working registers in the register file
• Added Stack Pointer Instructions table
• Restructured and improved documentation in the following sections:
  • Register File
  • X-, Y-, and Z-Registers
  • Accessing 16-bit Registers
• Added On-Chip Debug Capabilities section
• Updated bit names in the Status Register (SREG):
  • From Bit Copy Storage to Transfer Bit
  • From Sign Bit to Sign Flag

• Updated CLKOUT bit field in MCLKCTRLA register

• Updated Sleep Mode Activity Overview tables

• Updated Block Diagram figure
• Figures added:
  • MCU Start-up, RESET Tied to V_DD
  • Brown-out Detector Reset
  • External Reset Characteristics
  • Watchdog Reset
  • Software Reset
• Added Domains Affected By Reset section

• Added Minimum Interrupt Response Time table
• Updated bit field descriptions for:
  • CTRLA.IVSEL
  • LVL0PRI.LVL0PRI
• General improvement of the documentation and its structure

• Register names updated
  • From ASYNCCH to ASYNCCHn
  • From SYNCCH to SYNCCHn
  • From ASYNCUSER to ASYNCUSERn
  • From SYNCUSER to SYNCUSERn
• Bit field descriptions restructured
  • ASYNCCHn.ASYNCCH

• Updated Block Diagram figure
• Updated Signal Description table⁽¹⁾
• Added Peripheral Override section
• Added Asynchronous Sensing Pin Properties section
• Removed offset in the Available Interrupt Vectors and Sources table
• Added Event Generators in PORTx table
• General improvement of the documentation and its structure

• Updated Block Diagram figure
• Removed offset in the Available Interrupt Vectors and Sources table
• Name column added to bit field description tables:
  • CTRLA.ACTIVE
  • CTRLA.SLEEP
  • INTCTRL.VLMCFG

• Added the Clocks section
• Updated values in bit field descriptions:
  • CTRLA.WINDOW
  • CTRLA.PERIOD

• Updated Block Diagram figure
• Updated Timer/Counter Clock Logic figure
• Updated Signal Description table
• Added Offset Equation Overview table
• Added Offset When Counting Up figure
• Added Inverting Waveform Output figure
• Update Single-Slope Pulse-Width Modulation figure
• Added Single-Slope Pulse-Width Modulation in Split Mode figure
• Updated Timer/Counter Block Diagram Split Mode figure
• Added Event Generators in TCA table
• Added Event Users in TCA table
• Removed offset in the Available Interrupt Vectors and Sources in Normal Mode and Available Interrupt Vectors and Sources in Split mode tables
• Combined tables for the CTRLB.WGMODE bit field into one
• General improvement of the documentation and its structure

• Updated Block Diagram figure
• Added Timer/Counter Clock Logic figure
• Figures updated:
  • Periodic Interrupt Mode
  • Time-Out Check Mode
  • Input Capture on Event
  • Input Capture Frequency Measurement
  • Input Capture Pulse-Width Measurement
  • Input Capture Frequency and Pulse-Width Measurement
  • Single-Shot Mode
  • 8-Bit PWM Mode
• Added Event Generators in TCB table
• Added Event Users and Available Event Actions in TCB table
• Removed offset in the Available Interrupt Vectors and Sources table
• Name column added to bit field description tables:
  • CTRLA.CLKSEL
  • CTRLB.CNTMODE

• Updated Block Diagram figure
• Added Event Generators in RTC table
• Removed offset in the Available Interrupt Vectors and Sources table
• General improvement of the documentation and its structure

• Added information about TXD buffer in:
  • Block Diagram figure
  • Overview section
  • Data Transmission section
• Event Generators in USART table added
• Event Users in USART table added
• Offset in the Available Interrupt Vectors and Sources table removed
• Added CTRLD register
• General improvement of the documentation and its structure
• Updated terminology:
  • Master is replaced by host
  • Slave is replaced by client

• Updated Block Diagram figure
• Added Event Generators in SPI table
• Removed offset in the Available Interrupt Vectors and Sources table
• Interrupt Flags register separate for Normal and Buffer mode
• General improvement of the documentation and its structure
• Updated terminology:
  • Master is replaced by host
  • Slave is replaced by client

• Offset in the Available Interrupt Vectors and Sources table removed
• Name column added to bit field description tables:
  • CTRLA.FMPEN
  • MCTRLB.ACKACT
  • MCTRLB.MCMD
• General improvement of the documentation and its structure
• Updated terminology:
  • Master is replaced by host
  • Slave is replaced by client

• Offset in the Available Interrupt Vectors and Sources table removed

• Added Block Diagram figure
• Replaced Lookup Table Logic section with Truth Table Logic section
• Added Clock Source Settings section
• Updated bit field description of TRUTHn.TRUTHn

• Removed Low-Power Mode section

• Updated figures:
  • UPDI Clock Domains
  • UPDI Instruction Set Overview
  • LDS Instruction Operation
  • STS Instruction Operation
  • LD Instruction Operation
  • ST Instruction Operation
  • LCDS Instruction Operation
  • STCS Instruction Operation
  • REPEAT Instruction Operation
  • Inter Delay Example with LD and RPT
• Added sections:
  • BREAK in One-Wire mode
  • SYNCH and SYNCH in One-Wire mode
• Extended and improved the documentation related to enabling the UPDI peripheral
• Extended and improved the documentation related to disabling the UPDI peripheral
• Renamed the UPDI Enable with 12V Override of RESET pin section to UPDI Enable with High-Voltage Override of RESET pin
• Added the REPEAT Used With LD Instruction Operation figure
• Added Event Generators in UPDI table
• Removed implementation-specific details that are considered as not useful for the end users
• Updated bit field descriptions:
  • STATUSB.PESIG
  • ASI_RESET_REQ.RSTREQ

• Added Maximum Frequency vs. V_DD for [-40, 125]°C, Extended Temperature Range figure
• Added maximum numbers to the Power Consumption section
• Rounded numbers in the Peripherals Power Consumption table
• Updated TWI - Timing Requirements figure
• Updated numbers for t_OF in the TWI - Timing Characteristics table
• Added typical values for t_HD;STA, t_SU;STA, t_SU;STO and t_BUF
• Added SDA Hold Time table
• Updated Accuracy Characteristics table in ADC section
• Added TEMPSENSE section
• Updated tables in the AC section
• Added UPDI Max. Bit Rates vs. VDD table
• Replaced Chip Erase with Chip Erase with UPDI in the Programming Times table

• Added Temperature Sensor Error vs. Temperature ±3σ figure
• Added TWI SDA Hold Time vs. Temperature figure