ATtiny804/806/807/1604/1606/1607

5.1 Multiplexed Signals

Table 5-1. PORT Function Multiplexing, 14, 20 and 24 Pins
VQFN 24-Pin	VQFN 20-Pin	SOIC 20-Pin	SOIC 14-Pin	Pin Name^(1,2)	Other/Special	ADC0	AC0	USART0	SPI0	TWI0	TCA0	TCB0	CCL
23	19	16	10	PA0	RESET/UPDI	AIN0							LUT0-IN0
24	20	17	11	PA1		AIN1		TxD⁽³⁾	MOSI				LUT0-IN1
1	1	18	12	PA2	EVOUT0	AIN2		RxD⁽³⁾	MISO				LUT0-IN2
2	2	19	13	PA3	EXTCLK	AIN3		XCK⁽³⁾	SCK		WO3
3	3	20	14	GND
4	4	1	1	V_DD
5	5	2	2	PA4		AIN4		XDIR⁽³⁾	SS		WO4		LUT0-OUT
6	6	3	3	PA5		AIN5	OUT				WO5	WO
7	7	4	4	PA6		AIN6	AINN0
8	8	5	5	PA7		AIN7	AINP0						LUT1-OUT
9				PB7
10				PB6
11	9	6		PB5	CLKOUT	AIN8	AINP1				WO2⁽³⁾
12	10	7		PB4		AIN9	AINN1				WO1⁽³⁾		LUT0-OUT⁽³⁾
13	11	8	6	PB3				RxD			WO0⁽³⁾
14	12	9	7	PB2	EVOUT1			TxD			WO2
15	13	10	8	PB1		AIN10		XCK		SDA	WO1
16	14	11	9	PB0		AIN11		XDIR		SCL	WO0
17	15	12		PC0					SCK⁽³⁾			WO⁽³⁾
18	16	13		PC1					MISO⁽³⁾				LUT1-OUT⁽³⁾
19	17	14		PC2	EVOUT2				MOSI⁽³⁾
20	18	15		PC3					SS⁽³⁾		WO3⁽³⁾		LUT1-IN0
21				PC4							WO4⁽³⁾		LUT1-IN1
22				PC5							WO5⁽³⁾		LUT1-IN2

Note:

Pin names are of type Pxn, with x being the PORT instance (A, B) and n the pin number. The notation for signals is PORTx_PINn. All pins can be used as event input.
All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous detection.
Alternate pin positions. For selecting the alternate positions, refer to section PORTMUX - Port Multiplexer.

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