1.7.1 Synchronous Mode
Operation of TMR0 is incorrect when FOSC/4 is used as the clock source.
Work around
Clearing the T0ASYNC bit in the T0CON1 register when TMR0 is configured to use FOSC/4 may cause incorrect behavior. This issue is only valid when FOSC/4 is used as the clock source.
Affected Silicon Revisions
| A3 | A4 | ||||||
| X | X |