Silicon Issue Summary

Table . Silicon Issue Summary
ModuleFeatureItem No.Issue SummaryAffected Revisions
A3A4
Analog-to-Digital Converter (ADC)ADC ConversionADC ConversionDelay of one instruction cycle required prior to setting the ADGO bit when using ADCRC as the ADCC clock sourceX

ADCRC Oscillator Operation in Sleep

ADCRC Oscillator Operation in SleepThe ADCRC oscillator does not stop after conversion is complete in Sleep modeXX
ADC Conversion with FVRMissing Codes with FVR ReferenceUsing FVR as the ADC positive voltage reference can cause missing codesXX
ADC Conversion with FOSC as ClockADC GO Bit May Remain Set When the Clock Source is FOSCThe ADGO bit remains set when using FOSC as clock source with clock dividerXX
ADC operation in Burst Average ModeADCC Burst Average ModeThe ADCNT register does not increment past ’0b1’ in Burst Average mode with double sampling enabledXX
Double Sample ConversionsDouble Sample ConversionsAn unexpected acquisition time is added between the first and second conversionsXX
ADC Acquisition TimeADC Conversion Acquisition Time in Sleep (ADCC)Conversion during SLEEP mode when ADACQ=0 affects results on values in the upper half of the 10-bit range. The analog input is disconnected for 3-4 uS and the first bit of the result becomes zero.XX
ADC Short in Precharge StateADC Short in Pre-Charge StateADC shorts briefly in pre-charge state when the corresponding analog pin is selected as an outputXX
PIC18 Debug ExecutiveData Write Match BreakpointsData Write Match BreakpointsData write match breakpoints do not work when used on a location GSR spaceX
Single Step Function (SSTEP)Single Step Function Does Not Execute at SW BreakpointSingle Step function does not execute at SW BreakpointXX
PIC18 CoreTBLRDTBLRD Requires NVMREG Value to Point to Appropriate MemoryTBLRD requires NVMREG value to point to appropriate memoryX
Program Flash Memory (PFM)Endurance of PFM CellEndurance of PFM is Lower than SpecifiedEndurance of the PFM cell is lower than specifiedXX
Back to Back WritesPFM Back to Back WritesRepetitive writes may cause write/erase failuresXX
MSSPSMBus 2.0 Voltage LevelSMBus 2.0 Voltage LevelInput low-voltage threshold level is dependent on VDDXX
SPIMSSP SPI Client ModeSSPBUF may become corruptedXX
I2CSMBus 2.0 Voltage LevelAcknowledge failure on LF devices onlyX
Electrical SpecificationsMin VDD SpecificationMin VDD Specification (LF Devices Only)

VDDMIN specifications are changed for LF devices only for -40°C and 0°C

X
FVR SpecificationFVR - Fixed Voltage ReferenceFVR specifications require use above -20°CXX
Analog-to-Digital ConverterADC - Analog-to-Digital ConverterADC offset error specification is +/- 3.0 LSbXX
Timer0Clock SourceSynchronous ModeTMR0 does not function properly in Sync modeXX
Windowed Watchdog TimerWWDT Operation in Doze ModeWindow Operation in Doze ModeErroneous window violation error occurs in Doze modeXX
NVMNVMERR bit OperationNVMERRNVMERR bit is set incorrectly due to specific Reset eventsXX
Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)Transmit ModeDouble Byte TransmitPossible duplicate byte transmittedXX
Capture/Compare/PWM Module (CCP)PWM ModeWrong Duty Cycle for CCP ModuleDuty cycle values are incorrectXX
In-Circuit Serial ProgrammingLow-Voltage ProgrammingLow-Voltage Programming Not PossibleLow-Voltage Programming is not possible when VDD is below BORV while BOR is enabledXX
Note: Only those issues indicated in the last column apply to the current silicon revision.