5.1 Schematic Checklist

1

Verify the decoupling capacitor requirements are met for all power supply pins (VDD, VPMU_VDD, VPMU_VDD, AVDD).

2

Verify the decoupling capacitor requirements are met for all the BUCK power supply pins (BUCK_CLDO, BUCK_BB, BUCK_PLL and BUCK_LPA).

3

Verify the decoupling capacitor requirements are met for all the CLDO_O pins.

4

Verify the filtering requirement (Ferrite beads) for AVDD and power rail.

5

Verify the LC circuit components for DC-DC section is as per the recommendation, and verify that the same part numbers are being used.

6

Is GND paddle connected to GND?

7

Is power budgeting performed to ensure the power source is capable to supply the required current to the circuit in all functional conditions? It might be required to choose a power supply with maximum current handling at 125-130% of the estimated power budget.

8

Verify whether the chosen 16 MHz RF crystal meets the following requirements:

1. Frequency
2. Frequency tolerance including temperature and aging
3. Load capacitance requirements of both crystal and device

9

Verify the addition of the 32.768 kHz crystal to the design.

10

Verify that the design replicates the reference design for the RF section with same components and schematic.

11

Verify the addition of test points for the programming interface (SWDIO, SWDCLK, NMCLR, VDD, GND), critical power rails (VDD_1P35V and VDD_1P2V), RF and UART interface for regulatory testing (such as PA5 (TxD) and PA6 (RxD)).

13

Verify the addition of recommended bias resistor to pin 20 (EXTR).

14

Verify the addition of current limiting resistors for I/O pins interfaced to LED, buttons and so on.

15

Verify the addition of an RF shield placeholder in design.

16

For unused pins, review the recommendation and handle the pin status accordingly.