5.2 PCB Layout Checklist
S.No | Item Description | Verified (Yes/No) | Remarks |
|---|---|---|---|
1 | Verify whether the PCB stack-up matches with the reference design for achieving the best performance. | ||
2 | Verify that the decoupling capacitors for all power supply pins (VDD, VPMU_VDD, VPMU_VDD, AVDD), BUCK power supply pins (BUCK_CLDO, BUCK_BB, BUCK_PLL and BUCK_LPA) and CLDO_O are placed as close as possible to the IC pin. | ||
3 | Verify the PCB trace thickness for the power rail is adequate for the estimated current consumption. | ||
4 | Verify that all the decoupling capacitors have a dedicated GND via placed adjacent to the GND pad. Avoid sharing the GND via for different components. | ||
5 | Verify the loop formed PMU_BK, PMU switching inductor, decoupling capacitor and PMU_MLDO is as short as possible. Replicate this section of design as it is in the reference design. | ||
6 | Verify the addition of redundant vias for power rails and GND, wherever possible. | ||
7 | Verify that there are no signal or power traces routed in the Inner layer 1 (layer immediately below the device/RF traces). Dedicating this layer for GND is recommended. | ||
8 | Ensure the PCB routing topology for the 1P35V trace is as per the reference layout for achieving the best performance with the least IR voltage drop. | ||
9 | Verify the addition of grid of 4x4 vias with the recommended via size and spacing. | ||
10 | Verify with the PCB vendor and confirm that the single-ended impedance of RF trace is 50Ω. | ||
11 | Verify the placement of guard GND vias all around the RF trace. | ||
12 | Verify that there are no traces routed and no polygon pour split (such as, reference plane split) in all the layers under the RF routing area. | ||
13 | Verify that all the shunt components in the RF section use direct connect polygon style instead of the usual thermal relief polygon connect style. | ||
14 | Verify that the trace to crystal from the device pins is as short as possible and also covered with guard GND vias and polygon pour on either side to improve isolation. | ||
15 | Ensure the test points of critical power rails are sufficiently isolated from noise sources. | ||
16 | Verify the addition of placeholder RF shield footprint in the PCB layout. | ||
17 | Verify the addition of RF test point in the RF trace for production test. | ||
18 | Verify the addition of GND stitching vias in the entire board area wherever possible and at the PCB edges. | ||
19 | Verify there are no errors by running a Design Rule Checking (DRC) check provided by the CAD tool. |