5.2 Slave Mode

The LIN slave mode is configured using the following settings:

• Load the MODE [3:0] bits of the UxCON0 register with ‘0b1011’, placing the UART into LIN Slave mode.
• Set the Transmit Enable bit (TXEN) of the UxCON0 register to allow transmission.
• Set the Receive Enable bit (RXEN) of the UxCON0 register to allow reception.
• Clear the Transmit Polarity Control (TXPOL) bit of the UART Control Register 2 (UxCON2) to set the transmit polarity to a high Idle state.
• Clear the Receive Polarity Control (RXPOL) bit of the UxCON2 register to set the receive polarity to a high Idle state.
• Clear the two STP [1:0] bits of the UxCON2 register for one stop bit on both transmissions and receptions.
• Load the RxyPPS register (PPS output) with the TX pin selection code to map the TX output to the desired pin.
• Configure the UxRXPPS register to match the desired input pin.
• Clear the TRIS bit associated with the TX output pin.
• Set the TRIS bit associated with the RX input pin.
• Clear the ANSEL bit associated with the RX input pin.
• Set the Serial Port Enable (ON) bit of UxC.

The slave process will begin automatically upon the module receiving a Break over the LIN bus. At the end of the Break, the device will use the Sync byte to automatically configure the baud rate of the UART to match the master. The module will then automatically read the PID and store it in the receive FIFO. From that point on, it acts much in the same way as the Master/Slave mode example above: software must configure UxP2, UxP3, and the C0EN bit as predetermined by the PID, and will then transmit/receive the proper bytes from the transmit/receive FIFOs, as determined by the settings. The checksum is also automatically calculated on any received data, and if there is a checksum mismatch, the checksum error (CERIF) bit of UxERRIR will be set.