3.2.1.1 Pinout and Multiplexing

Table 3-1. 128-pin EP-TQFP Multiplexing
TQFP128 Pin Number	Power Rail/ Voltage Reference	Primary	Alternate		PIO Peripheral				Reset State	Comments
TQFP128 Pin Number	Power Rail/ Voltage Reference	Signal	Signal	Dir	Func	Signal	Dir	IO Set	Signal, Dir, PU, PD, HiZ, ST, FILTER	Comments
16	VDD3V3	PA0	–	–	A	FLEXCOM6_IO0	–	–	–
17	VDD3V3	PA1	–	–	A	FLEXCOM6_IO1	–	–	–
27	VDD3V3	PA2	WKUP3/TMP3	I	A	PCK1	O	1	PIO, I, PU, ST
27	VDD3V3	PA2	WKUP3/TMP3	I	B	TIOA0	I/O	2	PIO, I, PU, ST
28	VDD3V3	PA3	WKUP4/TMP4	I	A	TIOB0	I/O	2	PIO, I, PU, ST
29	VDD3V3	PA4	–	–	A	FLEXCOM0_IO0	I/O	1,2	PIO, I, PU, ST
30	VDD3V3	PA5	WKUP5	I	A	FLEXCOM0_IO1	I/O	1,2	PIO, I, PU, ST
31	VDD3V3	PA6	–	–	A	FLEXCOM0_IO2	I/O	1	PIO, I, PU, ST
					B	FLEXCOM0_IO4	O	2
					C	TIOA6	I/O	1
32	VDD3V3	PA7	–	–	A	FLEXCOM0_IO3	I/O	1,2	PIO, I, PU, ST
32	VDD3V3	PA7	–	–	C	TIOB6	I/O	1	PIO, I, PU, ST
5	VDD3V3	PA8	–	–	A	FLEXCOM1_IO0	I/O	1,2	PIO, I, PU, ST
6	VDD3V3	PA9	WKUP6	I	A	FLEXCOM1_IO1	I/O	1,2	PIO, I, PU, ST
25	VDD3V3	PA10	–	–	A	FLEXCOM1_IO2	I/O	1	PIO, I, PU, ST
					B	FLEXCOM1_IO4	O	2
					C	TCLK6	I	1
26	VDD3V3	PA11	–	–	A	FLEXCOM1_IO3	I/O	1,2	PIO, I, PU, ST
37	VDD3V3	PA12	–	–	A	FLEXCOM2_IO0	I/O	1,2	PIO, I, PU, ST
38	VDD3V3	PA13	WKUP7	I	A	FLEXCOM2_IO1	I/O	1,2	PIO, I, PU, ST
39	VDD3V3	PA14	–	–	A	FLEXCOM2_IO2	I/O	1	PIO, I, PU, ST
39	VDD3V3	PA14	–	–	B	FLEXCOM2_IO4	O	2	PIO, I, PU, ST
40	VDD3V3	PA15	–	–	A	FLEXCOM2_IO3	I/O	1,2	PIO, I, PU, ST
33	VDD3V3	PA16	–	–	A	FLEXCOM3_IO0	I/O	1,2	PIO, I, PU, ST
34	VDD3V3	PA17	–	–	A	FLEXCOM3_IO1	I/O	1,2	PIO, I, PU, ST
35	VDD3V3	PA18	–	–	A	FLEXCOM3_IO2	I/O	1	PIO, I, PU, ST
35	VDD3V3	PA18	–	–	B	FLEXCOM3_IO4	O	2	PIO, I, PU, ST
36	VDD3V3	PA19	–	–	A	FLEXCOM3_IO3	I/O	1,2	PIO, I, PU, ST
46	VDD3V3	PA20	–	–	A	PCK0	O	2	PIO, I, PU, ST
63	VDD3V3	PA21	–	–	A	COM0	O	1	PIO, I, PD, ST
63	VDD3V3	PA21	–	–	B	FLEXCOM5_IO3	I/O	5,6	PIO, I, PD, ST
64	VDD3V3	PA22	–	–	A	COM1	O	1	PIO, I, PD, ST
					B	FLEXCOM5_IO2	I/O	5
					C	FLEXCOM5_IO4	O	6
65	VDD3V3	PA23	–	–	A	COM2	O	1	PIO, I, PD, ST
					B	FLEXCOM5_IO1	I/O	5,6
					D	TCLK0	I	1
66	VDD3V3	PA24	–	–	A	COM3	O	1	PIO, I, PD, ST
					B	FLEXCOM5_IO0	I/O	5,6
					D	TIOB0	I/O	1
67	VDD3V3	PA25	–	–	A	COM4	O	1	PIO, I, PD, ST
					B	FLEXCOM6_IO0	I/O	4,5
					D	TIOA0	I/O	1
68	VDD3V3	PA26	–	–	A	COM5	O	1	PIO, I, PD, ST
68	VDD3V3	PA26	–	–	B	FLEXCOM6_IO1	I/O	4,5	PIO, I, PD, ST
69	VDD3V3	PA27	–	–	A	COM6	O	1	PIO, I, PD, ST
					B	FLEXCOM6_IO2	I/O	4
					C	FLEXCOM6_IO4	O	5
70	VDD3V3	PA28	–	–	A	COM7	O	1	PIO, I, PD, ST
70	VDD3V3	PA28	–	–	B	FLEXCOM6_IO3	I/O	4,5	PIO, I, PD, ST
71	VDD3V3	PA29	AD0/ ACC_INP0/ XIN	I	A	SEG0	O	1	PIO, I, PD, ST	Clock input when oscillator is in Bypass mode
					B	FLEXCOM0_IO4	O	1		ADCx/ACCx Signals: Pull-down must be disabled in PIO Controller when using these PIO pins as ADC/ACC inputs. XIN/OUT Signals: Pull-down must be disabled in PIO Controller when using these PIO pins as Crystal Oscillator XIN/XOUT signals.
					C	FLEXCOM1_IO4	O	1
					D	FLEXCOM2_IO4	O	1
72	VDD3V3	PA30	AD1/ACC_INP1	I	A	SEG1	O	1	PIO, I, PD, ST
74	VDD3V3	PB1	AD4/ACC_INN1	I	A	SEG4	O	1	PIO, I, PD, ST
					B	FLEXCOM7_IO3	I/O	1,2
					C	PCK1	O	2
					D	TCLK1	I	1
75	VDD3V3	PB0	AD3/ ACC_INN0/ XOUT	I/O	A	SEG3	O	1	PIO, I, PD, ST
					B	FLEXCOM3_IO4	O	1
					D	TIOB1	I/O	1
76	VDD3V3	PB2	ERASE	I	A	SEG5	O	1	ERASE, I, PD, ST
					B	FLEXCOM7_IO2	I/O	1
					C	FLEXCOM7_IO4	O	2
					D	TIOA2	I/O	1
77	VDD3V3	PA31	AD2/ACC_INP2	I	A	SEG2	O	1	PIO, I, PD, ST
77	VDD3V3	PA31	AD2/ACC_INP2	I	D	TIOA1	I/O	1	PIO, I, PD, ST
81	VDD3V3	PB3	–	–	A	SEG6	O	1	PIO, I, PD, ST
					B	FLEXCOM7_IO1	I/O	1,2
					D	TIOB2	I/O	1
82	VDD3V3	PB4	–	–	A	SEG7	O	1	PIO, I, PD, ST
					B	FLEXCOM7_IO0	I/O	1,2
					D	TCLK2	I	1
83	VDD3V3	PB5	–	–	A	SEG8	O	1	PIO, I, PD, ST
					B	FLEXCOM4_IO0	I/O	3,4
					C	TIOA5	I/O	1
84	VDD3V3	PB6	–	–	A	SEG9	O	1	PIO, I, PD, ST
					B	FLEXCOM4_IO1	I/O	3,4
					C	TIOB5	I/O	1
85	VDD3V3	PB7	–	–	A	SEG10	O	1	PIO, I, PD, ST
					B	FLEXCOM4_IO2	I/O	3
					C	FLEXCOM4_IO4	O	4
86	VDD3V3	PB8	–	–	A	SEG11	O	1	PIO, I, PD, ST
					B	FLEXCOM4_IO3	I/O	3,4
					C	TIOA3	I/O	1
87	VDD3V3	PB9	WKUP9	I	A	SEG12	O	1	PIO, I, PD, ST
87	VDD3V3	PB9	WKUP9	I	B	FLEXCOM3_IO0	I/O	3,4	PIO, I, PD, ST
88	VDD3V3	PB10	–	–	A	SEG13	O	1	PIO, I, PD, ST
					B	FLEXCOM3_IO1	I/O	3,4
					D	TRACESWO	O	1
89	VDD3V3	PB11	–	–	A	SEG14	O	1	PIO, I, PD, ST
					B	FLEXCOM3_IO2	I/O	3
					C	FLEXCOM3_IO4	O	4
90	VDD3V3	PB12	WKUP10	I	A	SEG15	O	1	PIO, I, PD, ST
90	VDD3V3	PB12	WKUP10	I	B	FLEXCOM3_IO3	I/O	3,4	PIO, I, PD, ST
91	VDD3V3	PB13	–	–	A	SEG16	O	1	PIO, I, PD, ST
91	VDD3V3	PB13	–	–	C	TIOB3	I/O	1,2	PIO, I, PD, ST
92	VDD3V3	PB14	–	–	A	SEG17	O	1	PIO, I, PD, ST
92	VDD3V3	PB14	–	–	C	TCLK3	I	1,2	PIO, I, PD, ST
93	VDD3V3	PB15	–	–	A	SEG18	O	1	PIO, I, PD, ST
93	VDD3V3	PB15	–	–	B	FLEXCOM5_IO4	O	1	PIO, I, PD, ST
94	VDD3V3	PB16	–	–	A	SEG19	O	1	PIO, I, PD, ST
94	VDD3V3	PB16	–	–	B	FLEXCOM6_IO4	O	1	PIO, I, PD, ST
95	VDD3V3	PB17	–	–	A	SEG20	O	1	PIO, I, PD, ST
95	VDD3V3	PB17	–	–	C	TCLK4	I	1,2	PIO, I, PD, ST
96	VDD3V3	PB18	–	–	A	SEG21	O	1	PIO, I, PD, ST
96	VDD3V3	PB18	–	–	C	TIOA4	I/O	1,2	PIO, I, PD, ST
97	VDD3V3	PB19	–	–	A	SEG22	O	1	PIO, I, PD, ST
97	VDD3V3	PB19	–	–	C	TIOB4	I/O	1,2	PIO, I, PD, ST
98	VDD3V3	PB20	–	–	A	SEG23	O	1	PIO, I, PD, ST
98	VDD3V3	PB20	–	–	B	FLEXCOM5_IO0	I/O	1,2	PIO, I, PD, ST
99	VDD3V3	PB21	–	–	A	SEG24	O	1	PIO, I, PD, ST
99	VDD3V3	PB21	–	–	B	FLEXCOM5_IO1	I/O	1,2	PIO, I, PD, ST
100	VDD3V3	PB22	–	–	A	SEG25	O	1	PIO, I, PD, ST
					B	FLEXCOM5_IO2	I/O	1
					C	FLEXCOM5_IO4	O	2
101	VDD3V3	PB23	–	–	A	SEG26	O	1	PIO, I, PD, ST
101	VDD3V3	PB23	–	–	B	FLEXCOM5_IO3	I/O	1,2	PIO, I, PD, ST
102	VDD3V3	PB24	–	–	A	SEG27	O	1	PIO, I, PD, ST
					B	FLEXCOM4_IO0	I/O	1,2
					C	TIOA5	I/O	2
103	VDD3V3	PB25	WKUP8	I	A	SEG28	O	1	PIO, I, PD, ST
					B	FLEXCOM4_IO1	I/O	1,2
					C	TIOB5	I/O	2
104	VDD3V3	PB26	–	–	A	SEG29	O	1	PIO, I, PD, ST
					B	FLEXCOM4_IO2	I/O	1
					C	FLEXCOM4_IO4	O	2
105	VDD3V3	PC0	–	–	A	SEG30	O	1	PIO, I, PD, ST
					B	FLEXCOM4_IO3	I/O	1,2
					C	TIOA3	I/O	2
					D	TDI	I	1
106	VDD3V3	PC1	–	–	A	SEG31	O	1	PIO, I, PD, ST
106	VDD3V3	PC1	–	–	B	FLEXCOM4_IO4	O	1	PIO, I, PD, ST
109	VDD3V3	PC2	–	–	A	SWCLK	I	1	SWCLK,ST
109	VDD3V3	PC2	–	–	B	FLEXCOM1_IO0	I/O	3	SWCLK,ST
110	VDD3V3	PC3	–	–	A	SWDIO	I/O	1	SWDIO,ST
110	VDD3V3	PC3	–	–	B	FLEXCOM1_IO1	I/O	3	SWDIO,ST
111	VDD3V3	PC4	–	–	–	–	I/O	–	PIO, I, PU, ST
112	VDD3V3	PC5	–	–	A	PCK2	O	1	PIO, I, PU, ST
112	VDD3V3	PC5	–	–	D	TCLK5	I	1,2	PIO, I, PU, ST
113	VDD3V3	PC6	–	–	A	FLEXCOM5_IO3	I/O	3,4	PIO, I, PU, ST
113	VDD3V3	PC6	–	–	B	FLEXCOM6_IO0	I/O	3	PIO, I, PU, ST
114	VDD3V3	PC7	WKUP11	I	A	FLEXCOM5_IO2	I/O	3	PIO, I, PU, ST
					B	FLEXCOM6_IO1	I/O	3
					C	FLEXCOM5_IO4	O	4
115	VDD3V3	PC8	–	–	A	FLEXCOM5_IO1	I/O	3,4	PIO, I, PU, ST
116	VDD3V3	PC9	WKUP12	I	A	FLEXCOM5_IO0	I/O	3,4	PIO, I, PU, ST
118	VDD3V3	PC10	–	–	A	QIO3	I/O	1	PIO, I, PU, ST
119	VDD3V3	PC11	–	–	A	QIO2	I/O	1	PIO, I, PU, ST
119	VDD3V3	PC11	–	–	B	FLEXCOM7_IO4	O	3	PIO, I, PU, ST
121	VDD3V3	PC12	–	–	A	QIO1	I/O	1	PIO, I, PU, ST
121	VDD3V3	PC12	–	–	B	FLEXCOM7_IO1	I/O	3	PIO, I, PU, ST
122	VDD3V3	PC13	–	–	A	QIO0	I/O	1	PIO, I, PU, ST
122	VDD3V3	PC13	–	–	B	FLEXCOM7_IO0	I/O	3	PIO, I, PU, ST
123	VDD3V3	PC14	WKUP13	I	A	QCS	O	1	PIO, I, PU, ST
					B	FLEXCOM7_IO3	I/O	3
					D	TIOA7	I/O	1
124	VDD3V3	PC15	–	–	A	QSCK	O	1	PIO, I, PU, ST
					B	FLEXCOM7_IO2	I/O	3
					D	TIOB7	I/O	1
125	VDD3V3	PC16	–	–	A	FLEXCOM6_IO0	I/O	1,2	PIO, I, PU, ST
125	VDD3V3	PC16	–	–	D	TCLK7	I	1	PIO, I, PU, ST
126	VDD3V3	PC17	–	–	A	FLEXCOM6_IO1	I/O	1,2	PIO, I, PU, ST
126	VDD3V3	PC17	–	–	D	TIOA8	I/O	1	PIO, I, PU, ST
127	VDD3V3	PC18	–	–	A	FLEXCOM6_IO2	I/O	1	PIO, I, PU, ST
					B	FLEXCOM6_IO4	O	2
					D	TIOB8	I/O	1
128	VDD3V3	PC19	–	–	A	FLEXCOM6_IO3	I/O	1,2	PIO, I, PU, ST
128	VDD3V3	PC19	–	–	D	TCLK8	I	1	PIO, I, PU, ST
1	VDD3V3	PC20	–	–	A	FLEXCOM7_IO1	I/O	4	PIO, I, PU, ST
2	VDD3V3	PC21	WKUP14	I	A	FLEXCOM7_IO0	I/O	4	PIO, I, PU, ST
3	VDD3V3	PC22	RTCOUT1	O	A	PCK0	O	1	PIO, I, PD, ST
4	VDD3V3	PD0	–	–	A	TIOA9	I/O	1	PIO, I, PU, ST
4	VDD3V3	PD0	–	–	B	–	I	1	PIO, I, PU, ST
42	VDD3V3	PD1	–	–	A	URXD, PWMFI0, PWMEXTRG1	I	1	PIO, I, PU, ST	PWMFI0 is enabled in PWM_FMR; PWMEXTRG1 is enabled in PWM_ETRGx (refer to section Pulse Width Modulation Controller (PWM))
42	VDD3V3	PD1	–	–	B	–	O	1	PIO, I, PU, ST
43	VDD3V3	PD2	–	–	A	UTXD	O	1	PIO, I, PU, ST
43	VDD3V3	PD2	–	–	B	–	I/O	1	PIO, I, PU, ST
7	VDD3V3	PD3	–	–	A	TCLK9	I	1	PIO, I, PU, ST
7	VDD3V3	PD3	–	–	C	PWMH0	O	1	PIO, I, PU, ST
8	VDD3V3	PD4	–	–	A	TIOB9	I/O	1	PIO, I, PU, ST
8		PD4	–	–	B	PCK2	O	2	PIO, I, PU, ST
9		PD5	–	–	A	MCSPI_SPCK	O	2,3,4	PIO, I, PU, ST
10		PD6	–	–	A	MCSPI_MISO	O	2	PIO, I, PU, ST
11		PD7	–	–	A	MCSPI_MOSI0	I	2,3,4	PIO, I, PU, ST
12		PD8	–	–	A	MCSPI_NPCS0	I/O	2,3	PIO, I, PU, ST
12			–	–	B	MCSPI_MOSI1	I	4	PIO, I, PU, ST
13		PD9	–	–	A	MCSPI_NPCS1	O	2,3	PIO, I, PU, ST
13			–	–	B	MCSPI_MOSI2	I	4	PIO, I, PU, ST
14		PD10	–	–	A	MCSPI_NPCS2	O	2,3	PIO, I, PU, ST
14			–	–	B	MCSPI_MOSI3	O	4	PIO, I, PU, ST
15		PD11	–	–	A	MCSPI_NPCS3	O	2,3	PIO, I, PU, ST
44	VDD3V3	PD12	–	–	A	URXD, PWMFI0, PWMEXTRG1	I	2	PIO, I, PU, ST	PWMFI0 is enabled in PWM_FMR; PWMEXTRG1 is enabled in PWM_ETRGx (refer to section Pulse Width Modulation Controller (PWM))
45	VDD3V3	PD13	–	–	A	UTXD	O	2	PIO, I, PU, ST
18	VDD3V3	PD14	–	–	A	TIOA10	I/O	1	PIO, I, PU, ST
19		PD15	–	–	A	TIOB10	I/O	1	PIO, I, PD, ST
19		PD15	–	–	B	PWMH1	O	1	PIO, I, PD, ST
20	VDD3V3	PD16	–	–	A	TCLK10	I	1	PIO, I, PD, ST
20	VDD3V3	PD16	–		B	PWMH2	O	1	PIO, I, PD, ST
22	VDD3V3	PD17	–	–	A	PWML0	O	1	PIO, I, PD, ST
22	VDD3V3	PD17	–		C	TIOA11	I/O	1	PIO, I, PD, ST
23	VDD3V3	PD18	–	–	A	PWML1	O	1	PIO, I, PD, ST
					B	–	I/O	1
					C	TIOB11, PWMEXTRG2	I/O	1		PWMEXTRG2 is enabled in PWM_ETRGx (refer to section Pulse Width Modulation Controller (PWM))
24	VDD3V3	PD19	–	–	A	PWML2	O	1	PIO, I, PD, ST
					B	–	O	1
					C	TCLK11	I	1
49	VDD3V3	NRST	–	I/O	–	–	–	–	I, PU, ST
57	VDDBU	FWUP	–	I	–	–	–	–	I,ST	Active low, external pull-up needed
58		JTAGSEL	–	I	–	–	–	–	I,PD
62		SHDN	–	O	–	–	–	–	O	0: The device is in Backup mode 1: The device is not in Backup mode
61		TST	–	I	–	–	–	–	I,PD	–
56		RTCOUT0	–	O	–	–	–	–	O	–
55		WKUP0/TMP0	–	I	–	–	–	–	I,ST	External pull-up needed
54		WKUP1/TMP1	–	I	–	–	–	–	I,ST	External pull-up needed
53		WKUP2/TMP2	–	I	–	–	–	–	I,ST	External pull-up needed
60		XOUT32	–	O	–	–	–	–	–	–
59		XIN32	–	I	–	–	–	–	–	Clock input when oscillator is in Bypass mode
21	VDD3V3	POWER	–	–	–	–	–	–	–	–
52	VBAT		–	–	–	–	–	–	–	–
51	VDD3V3		–	–	–	–	–	–	–	–
80	VDD3V3		–	–	–	–	–	–	–	–
108	VDD3V3		–	–	–	–	–	–	–	–
120	VDD3V3		–	–	–	–	–	–	–	–
41	VDDCORE		–	–	–	–	–	–	–	–
50	VDDCORE		–	–	–	–	–	–	–	–
107	VDDCORE		–	–	–	–	–	–	–	–
117	VDDCORE		–	–	–	–	–	–	–	–
78	VDDPLL		–	–	–	–	–	–	–	–
47	VDDOUT		–	–	–	–	–	–	–	–
48	VDD3V3		–	–	–	–	–	–	–	–
73	VREFP		–	–	–	–	–	–	–	–
79	VDDLCD		–	–	–	–	–	–	–	–
129	GND		–	–	–	–	–	–	–	Digital ground (exposed pad)