53 Revision History

Revision D - 09/2026

The following changes were implemented for this revision:


Section	Changes
Document	Removed ECDSA algorithm from Serial Boot Mode. Changed RTC_TAMPER to RTC_TCR.
Supply Controller (SUPC)	Changed IO to VDD3V3 in VDD3V3 Supply Monitor section and in bit 16 of SUPC_ISR register. Changed AUTO_IOSM to AUTO in bit 13 of SUPC_SMMR register.
Reset Controller (RSTC)	Changed SUPC_SMMR.IOSMPWRM to SUPC_SMMR.VDD3V3SMPWRM in VDDBU Power Switch Control section.
Peripheral DMA Controller (PDC)	Changed PERIPH_TCR and PERIPH_TNCR to PERIPH_RCR and PERIPH_RNCR, respectively, in Receive Buffer Full section.
Flexible Serial Communication Controller (FLEXCOM)	Changed FLEX_US_TCR, US_TNCR, and US_TCR to FLEX_US_RCR, US_RNCR, and US_RCR, respectively, in the RXBUFF bit of the FLEX_US_CSR (LIN_MODE) register.
Advanced Encryption Standard (AES)	Changed AES_MR.TMPCLR to AES_MR.TAMPCLR in Security and Safety Analysis and Reports section.
Advanced Encryption Standard Bridge (AESB)	Changed AESB_MR.TMPCLR to AESB_MR.TAMPCLR in Security and Safety Analysis and Reports section.
Multi Channel Serial Peripheral Interface (MCSPI)	Changed MCSPI_TWMR to MCSPI_TPMR in the TMCSMUX bit of the MCSPI_MR register.

Revision C - 03/2026

The following changes were implemented for this revision:


Section	Changes
Mechanical Characteristics	Updated figures.

Rev. B - 11/2022

Note: Microchip is in the process of implementing inclusive language in our documentation. During this update, you may see the old terms and the new terms in our documentation text. We apologize for any confusion.


Section	Changes
Minor editorial changes throughout.
Pinout and Multiplexing	Corrected pin 62 name.
Input/Output Lines	Shutdown (SHDN) Pin: corrected pin name.
Input/Output Lines	Flash Memory Hardware ERASE Signal: updated.
Memories	Application Core and Metrology Core Boot Process: updated.
ROM Code and Boot Strategies	GPNVM Bits Overview: updated table.
Supply Controller (SUPC)	SUPC_SR: index 12 now 'reserved'.
Clock Generator	PLL Controls: updated.
Power Management Controller (PMC)	Block Diagram: updated. Processor Clock Controller: updated. SysTick Clock: updated. Asynchronous Partial Wake-Up: Description updated. MCK0 Frequency Monitor: updated. Recommended Programming Sequence: updated. CPU Clock Switching Timings: updated. Main System Bus Clocks Switching Timings: updated. Updated bit names: PMC_SCER PMC_SCDR PMC_SCSR PMC_CPU_CKR PMC_IER PMC_IDR PMC_SR PMC_IMR PMC_PCR: index 19:16 now ‘reserved’.
Flexible Serial Communication Controller (FLEXCOM)	Throughout: Deleted references to Host High-Speed mode. Bus Clear Command, FIFO Pointer Error, FLEX_TWI_CR: modified Sniffer Mode: updated Sniffer description. FLEX_TWI_SMR: updated BSEL description.
Quad Serial Peripheral Interface (QSPI)	Corrected clock name from GCK to GCLK throughout.
Analog-to-Digital Converter (ADC) Controller	ADC_MR: updated reset value.
Analog Comparator Controller (ACC)	ACC_ISR: updated reset value.
True Random Number Generator (TRNG)	TRNG_WPSR: modified SWETYP description (value 5).
Pulse Width Modulation Controller (PWM)	Fault Protection: figure updated.
Electrical Characteristics	VDD3V3 Power-On-Reset: corrected unit in table. Analog Comparator Characterisitics: corrected unit in table.

Rev. A - 03/2022

First Issue.