11.1 Peripheral Identifiers
The table below defines the peripheral identifiers. A peripheral identifier is required for the control of the peripheral interrupt with the NVIC of the core, and for the control of the peripheral clock with the PMC.
The two Arm Cortex-M4 processors share the same interrupt mapping, and thus, they share the interrupts of the peripherals common to both cores.
To prevent any single software error from corrupting a peripheral's behavior, certain registers in the peripheral's address space can be write-protected. For further details, refer to the information on register write protection in the section of the corresponding peripheral, as well as to the section Register Write Protection in System Controller Write Protection (SYSCWP).
Each peripheral that has both a peripheral clock and a GCLK needs its peripheral clock enabled to work correctly. The GCLK alone is not sufficient.
Moreover, a minimum ratio between the peripheral clock (PCK) and the GCLK may be required (configuration of GCLK source, GCLKCSS, and GCLK ratio, GCLKDIV). For more information, refer to the corresponding peripheral section.
| Instance ID | Instance Name | NVIC Interrupt | PMC Clock Control | Generic Clock | Main System Bus Clock | Register Write Protection | Instance Description |
|---|---|---|---|---|---|---|---|
| 0 | SUPC | X | – | – | – | X | Supply Controller |
| 1 | RSTC | X | – | – | – | X | Reset Controller |
| 2 | RTC | X | – | – | – | X | Real Time Clock |
| 3 | RTT | X | – | – | – | X | Real Time Timer |
| 4 | WDT0 | X | – | – | – | X | Dual Watchdog Timer 0 |
| 5 | WDT1 | X | – | – | – | – | Dual Watchdog Timer 1 |
| 6 | PMC | X | – | – | – | X | Power Management Controller |
| 7 | SEFC0 | X | – | – | MCK0(1) | X | Embedded Flash Controller 0 |
| 8 | SEFC1 | X | – | – | MCK0(1) | X | Embedded Flash Controller 1 |
| 9 | FLEXCOM0 | X | X | X | MCK0DIV | X | FLEXCOM 0 (USART0/SPI0/TWI0) |
| 10 | FLEXCOM1 | X | X | X | MCK0DIV | X | FLEXCOM 1 (USART1/SPI1/TWI1) |
| 11 | FLEXCOM2 | X | X | X | MCK0DIV | X | FLEXCOM 2 (USART2/SPI2/TWI2) |
| 12 | FLEXCOM3 | X | X | X | MCK0DIV | X | FLEXCOM 3 (USART3/SPI3/TWI3) |
| 13 | FLEXCOM4 | X | X | X | MCK0DIV | X | FLEXCOM 4 (USART4/SPI4/TWI4) |
| 14 | FLEXCOM5 | X | X | X | MCK0DIV | X | FLEXCOM 5 (USART5/SPI5/TWI5) |
| 15 | FLEXCOM6 | X | X | X | MCK0DIV | X | FLEXCOM 6 (USART6/SPI6/TWI6) |
| 16 | FLEXCOM7 | X | X | X | MCK0DIV | X | FLEXCOM 7 (USART7/SPI7/TWI7) |
| 17 | PIOA | X | X | – | MCK0DIV | X | Application Core Parallel I/O Controller A (PIOA) |
| 18 | PIOA | SEC | – | – | MCK0DIV | X | Application Core Parallel I/O Controller A (PIOA) Secure Event Interrupt |
| 19 | PIOB | X | – | – | MCK0DIV | X | Application Core Parallel I/O Controller (B PIOB) |
| 20 | PIOB | SEC | – | – | MCK0DIV | X | Application Core Parallel I/O Controller (B PIOB) Secure Event Interrupt |
| 21 | PIOC | X | – | – | MCK0DIV | X | Application Core Parallel I/O Controller C (PIOC) |
| 22 | PIOC | SEC | – | – | MCK0DIV | X | Application Core Parallel I/O Controller C (PIOC) Secure Event Interrupt |
| 23 | QSPI | X | X | X | MCK0DIV | X | Quad IO Serial Peripheral Interface |
| 24 | ADC | X | X | X | MCK0DIV | X | Analog to Digital Converter |
| 25 | ACC | X | X | – | MCK0DIV | X | Analog Comparator |
| 26 | ARM0 | FPU | – | – | – | – | Floating Point Unit except IXC |
| 27 | ARM0 | IXC | – | – | – | – | FPU Interrupt IXC associated with FPU cumulative exception bit |
| 28 | IPC0 | X | X | – | MCK0DIV | X | Application Core Interprocessor Communication (IPC0) |
| 29 | SLCDC | X | – | – | – | X | Segment LCD Controller |
| 30 | MEM2MEM0 | X | X | – | MCK0DIV | X | Application Core Memory to Memory Transfer Controller (MEM2MEM0) |
| 31 | TC0 | CHANNEL0 | X | X | MCK0DIV | X | Timer Counter 0, Channel 0 |
| 32 | TC0 | CHANNEL1 | X | – | MCK0DIV | – | Timer Counter 0, Channel 1 |
| 33 | TC0 | CHANNEL2 | X | – | MCK0DIV | – | Timer Counter 0, Channel 2 |
| 34 | TC1 | CHANNEL0 | X | X | MCK0DIV | X | Timer Counter 1, Channel 0 |
| 35 | TC1 | CHANNEL1 | X | – | MCK0DIV | – | Timer Counter 1, Channel 1 |
| 36 | TC1 | CHANNEL2 | X | – | MCK0DIV | – | Timer Counter 1, Channel 2 |
| 37 | TC2 | CHANNEL0 | X | X | MCK0DIV | X | Timer Counter 2, Channel 0 |
| 38 | TC2 | CHANNEL1 | X | – | MCK0DIV | – | Timer Counter 2, Channel 1 |
| 39 | TC2 | CHANNEL2 | X | – | MCK0DIV | – | Timer Counter 2, Channel 2 |
| 40 | TC0 | C0SEC | – | – | MCK0DIV | X | Timer Counter 0, Channel 0, Secure IRQ |
| 41 | TC0 | C1SEC | – | – | MCK0DIV | – | Timer Counter 0, Channel 1, Secure IRQ |
| 42 | TC0 | C2SEC | – | – | MCK0DIV | – | Timer Counter 0, Channel 2, Secure IRQ |
| 43 | TC1 | C0SEC | – | – | MCK0DIV | X | Timer Counter 1, Channel 0, Secure IRQ |
| 44 | TC1 | C1SEC | – | – | MCK0DIV | – | Timer Counter 1, Channel 1, Secure IRQ |
| 45 | TC1 | C2SEC | – | – | MCK0DIV | – | Timer Counter 1, Channel 2, Secure IRQ |
| 46 | TC2 | C0SEC | – | – | MCK0DIV | X | Timer Counter 2, Channel 0, Secure IRQ |
| 47 | TC2 | C1SEC | – | – | MCK0DIV | – | Timer Counter 2, Channel 1, Secure IRQ |
| 48 | TC2 | C2SEC | – | – | MCK0DIV | – | Timer Counter 2, Channel 2, Secure IRQ |
| 49 | AES | X | X | – | MCK0DIV | X | Advanced Encryption Standard |
| 50 | AES | AESSEC | – | – | MCK0DIV | – | AES Secure Event Interrupt |
| 51 | AESB | X | X | – | MCK0DIV | X | AES Bridge |
| 52 | AESB | AESBSEC | – | – | MCK0DIV | X | AES Bridge Secure Interrupt |
| 53 | SHA | X | X | – | MCK0DIV | X | Secure Hash Algorithm |
| 54 | SHA | SHASEC | – | – | MCK0DIV | – | SHA Secure Event Interrupt |
| 55 | TRNG | X | X | – | MCK0DIV | X | True Random Number Generator |
| 56 | TRNG | TRNGSEC | – | – | MCK0DIV | – | TRNG Secure Event Interrupt |
| 57 | ICM | X | X | – | MCK0DIV | X | Integrity Check Module |
| 58 | ICM | ICMSEC | – | – | MCK0DIV | X | Integrity Check Module |
| 59 | CPKCC | X | X | – | MCK0 | – | Public Key Cryptography Controller |
| 60 | MATRIX0 | X | – | – | MCK0 | X | High-Speed Application Core Matrix (MATRIX0) |
| 61 | MATRIX1 | X | – | – | MCK0DIV | X | Low-Speed Application Core Matrix (MATRIX1) |
| 62 | SUPC | WKUP3 | – | – | – | – | External interrupt 3 |
| 63 | SUPC | WKUP4 | – | – | – | – | External interrupt 4 |
| 64 | SUPC | WKUP5 | – | – | – | – | External interrupt 5 |
| 65 | SUPC | WKUP6 | – | – | – | – | External interrupt 6 |
| 66 | SUPC | WKUP7 | – | – | – | – | External interrupt 7 |
| 67 | SUPC | WKUP8 | – | – | – | – | External interrupt 8 |
| 68 | SUPC | WKUP9 | – | – | – | – | External interrupt 9 |
| 69 | SUPC | WKUP10 | – | – | – | – | External interrupt 10 |
| 70 | SUPC | WKUP11 | – | – | – | – | External interrupt 11 |
| 71 | SUPC | WKUP12 | – | – | – | – | External interrupt 12 |
| 72 | SUPC | WKUP13 | – | – | – | – | External interrupt 13 |
| 73 | SUPC | WKUP14 | – | – | – | – | External interrupt 14 |
| 74 | – | – | – | – | – | – | – |
| 78 | MEM2MEM1 | X | X | – | MCK1DIV | X | Metrology Core Memory to Memory Transfer Controller 1 (MEM2MEM1) |
| 79 | TC3 | CHANNEL0 | X | X | MCK0DIV | X | Timer Counter 3, Channel 0 |
| 80 | TC3 | CHANNEL1 | X | – | MCK0DIV | X | Timer Counter 3, Channel 1 |
| 81 | TC3 | CHANNEL2 | X | – | MCK0DIV | X | Timer Counter 3, Channel 2 |
| 82 | TC3 | C0SEC | – | – | MCK0DIV | X | Timer Counter 3, Channel 0, Secure IRQ |
| 83 | TC3 | C1SEC | – | – | MCK0DIV | – | Timer Counter 3, Channel 1, Secure IRQ |
| 84 | TC3 | C2SEC | – | – | MCK0DIV | – | Timer Counter 3, Channel 2, Secure IRQ |
| 85 | PIOD | X | X | – | MCK1DIV | – | Metrology Core Parallel I/O Controller D (PIOD) |
| 86 | PIOD | SEC | – | – | MCK1DIV | X | Metrology Core Parallel I/O Controller D Secure Interrupt (named PIOD) |
| 87 | UART | X | X | X | MCK1DIV | X | Optical UART |
| 88 | IPC1 | X | X | – | MCK1DIV | – | Metrology Core Interprocessor Communication (IPC1) |
| 89 | MCSPI | X | X | X | MCK1DIV | X | Multi-Channel SPI |
| 90 | PWM | X | X | – | MCK1DIV | – | Pulse Width Modulation |
| 91 | SRAM1 | – | X | – | MCK1 | – | Metrology Core RAM (SRAM 1 & 2) |
| 92 | ARM1 | FPU | – | – | – | – | Metrology Core (CORE1) Floating Point Unit except IXC |
| 93 | ARM1 | IXC | – | – | – | – | Metrology Core (CORE1) FPU Interrupt IXC associated with FPU cumulative exception bit |
| 94 | MATRIX2 | X | – | – | MCK1 | X | High-SpeedMetrology Core Matrix (MATRIX2) |
| 95 | MATRIX3 | X | – | – | MCK1DIV | X | Low-Speed Metrology Core Matrix (MATRIX3) |
Note:
- SEFC0/SEFC1 clocks are MCK0DIV2 clock after power-up and reset and during the whole execution of the ROM Code. The end user application must set the SEFC clock to CPU clock (MCK0) for maximum performance. Refer to the Flash configuration register SFR_FLASH in the section Special Function Registers (SFR).