15.4.4 VDD3V3 Supply Monitor
The SUPC embeds a supply monitor which monitors the VDD3V3 rail.
The VDD3V3 supply monitor can be used to prevent the processor from entering an unpredictable state if the main power supply drops below a certain level.
The threshold of the VDD3V3 supply monitor is programmable in the VDD3V3SMTH field of the Supply Monitor Mode Register (SUPC_SMMR). Refer to the section “Electrical Characteristics”.
The VDD3V3 supply monitor can also be enabled for one slow clock period out of every 32, 256, or 2048 slow clock periods, depending on the user’s selection. This is configured in the VDD3V3SMSMPL field in SUPC_SMMR.
Enabling the VDD3V3 supply monitor for such reduced times divides the typical supply monitor power consumption by factors of 2, 16, and 128, respectively, if continuous monitoring of the VDD3V3 power supply is not required.
A VDD3V3 supply monitor detection generates either a reset of the VDDCORE domain or a wake-up (exit from Backup mode). Generating a VDDCORE domain reset when a VDD3V3 supply monitor detection occurs is enabled by writing SUPC_SMMR.VDD3V3SMRSTEN = 1.
Waking up the device when a VDD3V3 supply monitor event occurs can be enabled by writing VDD3V3SMWKEN = 1 in the Backup Mode register (SUPC_BMR).
A VDD3V3 supply monitor undervoltage event can trigger an interrupt by writing VDD3V3SMEV = 1 in the Interrupt Enable register (SUPC_IER).
The SUPC provides the following status bit:
- SUPC_SR.VDD3V3SMWS: The flag is raised when a VDD3V3 supply monitor event triggers a wake-up of the system. This flag is a copy of VDD3V3SMWS in the Wakeup Status Register (SUPC_WUSR) and thus is cleared when SUPC_WUSR is read.
- SUPC_SR.VDD3V3SMRSTS: The flag is raised when a VDD3V3 supply monitor undervoltage event triggers a VDDCORE reset. This flag is a copy of SUPC_WUSR.VDD3V3SMRSTS and thus is cleared when SUPC_WUSR is read.
- SUPC_SR.VDD3V3SMS: VDD3V3 supply monitor output.
- SUPC_SR.VDD3V3SMIS: The flag rises when a VDD3V3 supply monitor
undervoltage event occurs. This flag is a copy of SUPC_ISR.VDD3V3SMEV and is cleared
when the SUPC_ISR is read.
Figure 15-2. VDD3V3 Supply Monitor Status Bit and Associated Interrupt
