6.1 Device Addressing

Accessing the device requires an 8‑bit device address byte following a Start condition to enable the device for a read or write operation. Since multiple client devices can reside on the serial bus, each client device must have its own unique address so the host can access each device independently.

The Most Significant four bits of the device address byte is referred to as the device type identifier. The device type identifier ‘1010’ (Ah) is required in bits 7 through 4 of the device address byte (see Table 6-1).

Following the 4-bit device type identifier are the hardware client address bits, A2, A1 and A0. These bits can be used to expand the address space by allowing up to eight Serial EEPROM devices on the same bus. These hardware client address bits must correlate with the voltage level on the corresponding hardwired device address input pins A0, A1 and A2. The A0, A1 and A2 pins use an internal proprietary circuit that automatically biases the pin to a logic ‘0’ state if the pin is allowed to float. In order to operate in a wide variety of application environments, the pull‑down mechanism is intentionally designed to be somewhat strong. Once the pin is biased above the CMOS input buffer's trip point (~0.5 x V_CC), the pull‑down mechanism disengages. Microchip recommends connecting the A0, A1 and A2 pins to a known state whenever possible.

The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon the successful comparison of the device address byte, the AT24C256C will return an ACK. If a valid comparison is not made, the device will NACK.

For all operations except the current address read, two 8‑bit word address bytes must be transmitted to the device immediately following the device address byte. The word address bytes consist of the 15‑bit memory array word address, and are used to specify which byte location in the EEPROM to start reading or writing.

The first word address byte contains the seven Most Significant bits of the word address (A14 through A8) in bit positions six through zero, as seen in Table 6-2. Bit 7 of the first word address byte is a “don't care” bit as it is outside of the addressable 256‑Kbit range. Upon completion of the first word address byte, the AT24C256C will return an ACK.

Next, the second word address byte is sent to the device which provides the remaining eight bits of the word address (A7  through A0). Upon completion of the second word address byte, the AT24C256C will return an ACK. See Table 6-3 to review these bit positions.