1.6.1 Changing the Timer1 Gate Source May Cause Unexpected Interrupts
When a new value is written into the Timer1 Gate Source Select (GSS) bits of the TxGATE register, the TMRxGIF interrupt flag may be set unexpectedly, and if the TMRxGIE bit is set, an unexpected interrupt will occur.
Work around
User software must clear the TMRxGIF bit immediately after writing the new value to the GSS bits.
Affected Silicon Revisions
| A1 | A3 |
| X |