The PIC18F24/25Q24 devices that you have received conform functionally to the current device data sheet (DS40002517B), except for the anomalies described in this document.

The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in the table below.

The errata described in this document will be addressed in future revisions of the PIC18F24/25Q24 silicon.

Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current.
Table . Silicon Device Identification
Part Number Device ID Revision ID
A1 D1
PIC18F24Q24 0x78A0 0xA001 0xA0C1
PIC18F25Q24 0x78C0 0xA001 0xA0C1
Important: Refer to the Device/Revision ID section in the current “PIC18-Q24 Family Programming Specification” (DS40002414) for more detailed information on Device Identification and Revision IDs for your specific device.
Table . Silicon Issue Summary
Module Feature Item No. Issue Summary Affected Revisions
A1 D1
Universal Timer Module Level-triggered ERS Start/Reset condition 1.1.1  Dead zone exists in level-triggered Start/Reset condition when ERS signal is generated due to an SFR access X X
Interrupts 1.1.2  Interrupts do not work when leaving Debug mode X X
Multi-Voltage I/O VDDIOx I/O Monitor Disable 1.2.1  VDDIOx I/O Monitor Disable feature causes adverse MVIO module behavior X
MVIO Low-Voltage Detect output status bit 1.2.2  VDDIOx Low Voltage Detect Status bit does not return LVD status X
I2C Host Data Request (MDR) bit 1.3.1  MDR bit is not cleared after Bus Time-Out X
Bus Time-Out 1.3.2  Bus Time-Out not detected properly when External Host Clock stretches X
Clock Stretch Disable 1.3.3  Clock Stretch Disable not working properly X
Bus Time-Out 1.3.4  Bus Time-Out causes false Start/Stop X
Multi-Host Mode 1.3.5  Multi-Host Mode will cause Bus failures X X
Bus Time-Out 1.3.6  CSTR bit is not cleared after Bus Time-Out X
Bus Collision 1.3.7  Bus Collision followed by a Stop during a transaction by an external Host device may hang the bus X X
Multi-Host Mode 1.3.8  Module may hang the I2C bus during Multi-Host arbitration X X
Bus Free Time 1.3.9  The Bus Free Divider Ratio BFREDR = 1 value is not functional X
Oscillator Secondary Oscillator (SOSC) 1.4.1  SOSC does not function when the device is configured to run from an external oscillator X
Comparator Ultra-Low Power (UPL) Operation 1.5.1  Comparator module will not function in ULP mode X
Timer1 Timer1 Gate Source 1.6.1  Changing the Timer1 gate source may cause unexpected interrupts X
Note: Only those issues indicated in the last column apply to the current silicon revision.