The SPI module features a transfer counter that allows users the ability to configure how many data transfers will occur in a given transaction. The transfer counter is comprised of the SPIxTCNT registers and is partially controlled using the SPIxTWIDTH register. The transfer counter can operate in two different modes, depending on the configuration of the Bit-Length Mode Select (BMODE) bit. Regardless of the BMODE setting, the TCZIF interrupt flag will be set when the transfer counter decrements to zero. Rather than writing a software loop that controls the number of SPI transfers that occur within a given data transaction, the transfer counter can be configured to do the same thing in hardware, which eliminates the need for software intervention, freeing up the CPU.
Although the transfer counter can control the amount of data and the bit-length of data being transferred by the SPI module, there are still other requirements that must be met for subsequent transmission and reception to occur without disruption. Data will only be transmitted if the Transmit FIFO (TXFIFO) has data written to it and new data will not be received if the Receive FIFO (RXFIFO) is not empty. The user must ensure that any received data is read from the buffer so that it can be cleared to receive new data. The behavior of the transfer counter and SPI module is dependent on the status of the BMODE Configuration bit.