mtvec)By default, all interrupts trap to a single address defined in the
mtvec register. The interrupt handler must read mcause
and handle the trap accordingly. The CPU Core Complex supports interrupt vectoring for
defining an interrupt handler for each interrupt defined in mie. Interrupt
vectoring enables all local interrupts to trap to exclusive interrupt handlers. With
vectoring enabled, all global interrupts trap to a single global interrupt vector. Vectored
interrupts are enabled when the MODE field of the mtvec
register is set to 1. The following table lists the mtvec register
description.
| Bits | Field Name | Attributes | Description |
|---|---|---|---|
| [1:0] | MODE | WARL | MODE determines whether or not interrupt
vectoring is enabled. The field encoding of
0: (Direct) All exceptions set PC to BASE 1: (Vectored) Asynchronous interrupts set PC to BASE + 4 × cause ≥2: Reserved |
| [63:2] | BASE[63:2]1 | WARL | Interrupt Vector Base Address. Must be aligned on a 128-byte boundary when MODE=1. |
1. BASE[1:0] is not present in this register and is implicitly 0.
If vectored interrupts are disabled (mtvec.MODE=0), all
interrupts trap to the mtvec.BASE address. If vectored interrupts are
enabled (mtvec.MODE=1), interrupts set the PC to mtvec.BASE + 4 ×
exception code. For example, if a machine timer interrupt is taken, the PC is
set to mtvec.BASE + 0x1C. The trap vector table is populated with jump
instructions to transfer control to interrupt-specific trap handlers. In Vectored Interrupt
mode, BASE must be 128-byte aligned. All machine Global interrupts are mapped to exception
code of 11. Thus, when interrupt vectoring is enabled, the PC is set to address
mtvec.BASE + 0x2C for any Global interrupt. See the interrupt exception
codes table in Machine Cause Register (mcause).