Supervisor Trap Vector (stvec)

By default, all interrupts defined in sie trap to a single address defined in the stvec register. The interrupt handler must read scause and handle the interrupt accordingly. The CPU Core Complex supports interrupt vectors, which enables each interrupt to trap to its own specific interrupt handler. Vectored interrupts can be enabled by setting the stvec.MODE field to 1.

Table 1. Supervisor Trap Vector Register (`stvec`)
Bits	Field Name	Attributes	Description
[1:0]	MODE	WARL	MODE determines whether or not interrupt vectoring is enabled. The field encoding of `stvec.MODE` is as follows: 0: (Direct) All exceptions set PC to BASE 1: (Vectored) Asynchronous interrupts set PC to: BASE + 4 × cause. ≥2: Reserved
[63:2]	BASE[63:2]	WARL	Interrupt Vector Base Address. Must be aligned on a 128-byte boundary when MODE=1. Note: BASE [1:0] is not present in this register and is implicitly 0.

If vectored interrupts are disabled (stvec.MODE=0), all interrupts trap to the stvec.BASE address. If vectored interrupts are enabled (stvec.MODE=1), interrupts set the PC to stvec.BASE + 4 × exception code. For example, if a supervisor timer interrupt is taken, the PC is set to stvec.BASE + 0x14. Typically, the trap vector table is populated with jump instructions to transfer control to interrupt-specific trap handlers. In Vectored Interrupt mode, BASE must be 128-byte aligned.

All supervisor Global interrupts are mapped to exception code of 9. Thus, when interrupt vectoring is enabled, the PC is set to address stvec.BASE + 0x24 for any global interrupt. See the supervisor interrupt exception codes in Table 2.