The device has three Fuse bytes. The
following tables describe briefly the functionality of all the fuses and how they are
mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are
programmed.
Table 1. Extended Fuse Byte for ATmega328PB
| Extended Fuse
Byte |
Bit
No. |
Description |
Default
Value |
| – |
7 |
– |
1 |
| – |
6 |
– |
1 |
| – |
5 |
– |
1 |
| – |
4 |
– |
1 |
| CFD
|
3 |
Disable Clock Failure Detection |
0 (programmed, CFD disable) |
| BODLEVEL2(1) |
2 |
Brown-out
Detector trigger level |
1
(unprogrammed) |
| BODLEVEL1(1) |
1 |
Brown-out
Detector trigger level |
1
(unprogrammed) |
| BODLEVEL0(1) |
0 |
Brown-out
Detector trigger level |
1
(unprogrammed) |
Note:
- 1.Refer to Table BODLEVEL Fuse Coding
in System and Reset Characteristics for BODLEVEL Fuse decoding.
Table 2. Fuse High Byte
| High Fuse
Byte |
Bit
No. |
Description |
Default
Value |
| RSTDISBL(1) |
7 |
External Reset
Disable |
1
(unprogrammed) |
| DWEN |
6 |
debugWIRE
Enable |
1
(unprogrammed) |
| SPIEN(2) |
5 |
Enable Serial
Program and Data Downloading |
0 (programmed,
SPI programming enabled) |
| WDTON(3) |
4 |
Watchdog Timer
Always On |
1
(unprogrammed) |
| EESAVE |
3 |
EEPROM memory
is preserved through the Chip Erase |
1
(unprogrammed), EEPROM not preserved |
| BOOTSZ1 |
2 |
Select Boot
Size
(see Boot Loader Parameters) |
0
(programmed)(4) |
| BOOTSZ0 |
1 |
Select Boot
Size
(see Boot Loader Parameters) |
0
(programmed)(4) |
| BOOTRST |
0 |
Select Reset
Vector |
1
(unprogrammed) |
Note:
- 1.Refer to Alternate Functions of
Port C in I/O-Ports chapter for description of RSTDISBL Fuse.
- 2.The SPIEN Fuse is not accessible
in serial programming mode.
- 3.Refer to WDTCSR – Watchdog
Timer Control Register for details.
- 4.The default value of BOOTSZ[1:0] results in maximum
Boot Size. See table Boot Size Configuration in subsection Boot Loader
Parameters in the previous chapter for details.
Table 3. Fuse Low Byte
| Low Fuse
Byte |
Bit
No. |
Description |
Default
Value |
| CKDIV8(4) |
7 |
Divide clock
by 8 |
0
(programmed) |
| CKOUT(3) |
6 |
Clock
output |
1
(unprogrammed) |
| SUT1 |
5 |
Select
start-up time |
1
(unprogrammed)(1) |
| SUT0 |
4 |
Select
start-up time |
0
(programmed)(1) |
| CKSEL3 |
3 |
Select Clock
source |
0
(programmed)(2) |
| CKSEL2 |
2 |
Select Clock
source |
0
(programmed)(2) |
| CKSEL1 |
1 |
Select Clock
source |
1
(unprogrammed)(2) |
| CKSEL0 |
0 |
Select Clock
source |
0
(programmed)(2) |
Note:
- 1.The default value of SUT[1:0]
results in maximum start-up time for the default clock source. See table Start-Up
Times for the Internal Calibrated RC Oscillator Clock Selection - SUT in
Calibrated Internal RC Oscillator of System Clock and Clock Options
chapter for details.
- 2.The default setting of CKSEL[3:0]
results in internal RC Oscillator @ 8 MHz. See table Internal Calibrated RC
Oscillator Operating Modes in Calibrated Internal RC Oscillator of the
System Clock and Clock Options chapter for details.
- 3.The CKOUT Fuse allows the system
clock to be output on PORTB0. Refer to Clock Output Buffer section in the
System Clock and Clock Options chapter for details.
- 4.Refer to System Clock
Prescaler section in the System Clock and Clock Options chapter for
details.
The status of the Fuse bits is not affected
by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program
the Fuse bits before programming the Lock bits.