The UTMR module offers three interrupts and DMA triggers:
- 1.Period Match Interrupt – occurs when
a PR match condition is generated.(1)
- 2.Zero Interrupt – occurs when timer counter value becomes zero either because of a
Reset condition, rollover, or software clear.
- 3.Capture Interrupt – occurs when a
capture event is generated.(2)
Each of these interrupts has separate interrupt enable and flag bits in the
timer module (PRIE/PRIF, ZIE/ZIF, CIE/CIF), which are combined together to have one top
system level interrupt (TUxyIE/TUxyIF) in the PIRx register.
Important:
- 1.A PR match condition is
generated only when the timer counter increments from PR-1 to PR. The
condition is not triggered when the user writes the PR value directly to the
counter.
- 2.Refer to Timer, Capture and Period Registers for details
about the different capture events.