Timer, Capture and Period Registers

The n-bit timer/counter register (TUxyTMR) is the actual register that contains the timer value. This value increments at every timer clock tick. Use the CPOL bit to select the active timer clock edge. The TUxyTMR timer/counter register is not double buffered in hardware and no read/write protection is offered in hardware. Hence, the user is encouraged to access or alter the timer value only using the capture and period registers described below. The raw counter may be directly accessed, but the access is not double buffered and may corrupt the data.

The n-bit period register (TUxyPR) contains the value that determines the period of the timer. At every timer clock tick, the value in the TUxyTMR timer counter register is compared to the TUxyPR period register. When the TUxyTMR timer counter value increments from PR-1 to PR, a period register match (PR match) condition is generated. The TUxyPR period register is double buffered in hardware to allow the user to change the period of the timer while the timer is running. To change the period while the timer is running, write to the higher bytes of the TUxyPR register first (does not apply in 8-bit configuration of the module), which buffers the new data. Then write to the least significant byte of the TUxyPR register to arm the buffer to be loaded. Once the buffer is armed, an upcoming Reset event will load the new period value.

The n-bit capture register (TUxyCR) is a read-only register that is provided to safely and atomically read the value of the timer counter. Any of the following capture events will capture the timer counter value in that instant (clock synchronization delay applies) and store it in the TUxyCR capture register.

1. 1.Setting the CAPT command bit.
2. 2.When STOP ≠ None, the timer value is captured whenever a stop event is generated.
3. 3.When STOP = None, the timer value is captured at every rising edge of the ERS signal (or falling ERS edge if EPOL = 1). Refer to Table 1-3 for more information.

Both TUxyTMR timer counter and the TUxyCR capture registers share the same memory address. When RDSEL = 1, the TUxyTMR timer counter register is accessed to read, and when RDSEL = 0, the TUxyCR capture register is accessed to read. The TUxyCR capture register gets updated whenever a capture event occurs regardless of the RDSEL bit setting.