SSC Transmit Clock Mode Register
This register can only be written if the WPEN bit is cleared in the SSC Write Protection Mode Register.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| PERIOD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| STTDLY[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| START[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CKG[1:0] | CKI | CKO[2:0] | CKS[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Transmit Clock Selection
| Value | Name | Description |
|---|---|---|
| 0 | MCK | Divided Clock |
| 1 | RK | RK Clock signal |
| 2 | TK | TK pin |
Transmit Clock Output Mode Selection
| Value | Name | Description |
|---|---|---|
| 0 | NONE | None, TK pin is an input |
| 1 | CONTINUOUS | Continuous Transmit Clock, TK pin is an output |
| 2 | TRANSFER | Transmit Clock only during data transfers, TK pin is an output |
Transmit Clock Inversion
CKI affects only the Transmit Clock and not the Output Clock signal.
| Value | Description |
|---|---|
| 0 | The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame Sync signal input is sampled on Transmit Clock rising edge. |
| 1 | The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame Sync signal input is sampled on Transmit Clock falling edge. |
Transmit Clock Gating Selection
| Value | Name | Description |
|---|---|---|
| 0 | CONTINUOUS | None |
| 1 | EN_TF_LOW | Transmit Clock enabled only if TF Low |
| 2 | EN_TF_HIGH | Transmit Clock enabled only if TF High |
Transmit Start Selection
| Value | Name | Description |
|---|---|---|
| 0 | CONTINUOUS | Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data |
| 1 | RECEIVE | Receive start |
| 2 | TF_LOW | Detection of a low level on TF signal |
| 3 | TF_HIGH | Detection of a high level on TF signal |
| 4 | TF_FALLING | Detection of a falling edge on TF signal |
| 5 | TF_RISING | Detection of a rising edge on TF signal |
| 6 | TF_LEVEL | Detection of any level change on TF signal |
| 7 | TF_EDGE | Detection of any edge on TF signal |
Transmit Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the current start of transmission of data. When the transmitter is programmed to start synchronously with the receiver, the delay is also applied.
If STTDLY is too short with respect to transmit synchronization data (SSC_TSHR), SSC_THR.TDAT is transmitted instead of the end of SSC_TSHR.
Transmit Period Divider Selection
This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 × (PERIOD + 1) Transmit Clock.