To represent the AVR DB functionality, two of the AVR DB op amp models are configured as cascading non-inverting PGA as in software. The output from OP2 is connected to a generic Analog Comparator (AC) representing the AC in the AVR DB. The AC is also connected to a voltage source, AC_Trigger_lvl1, which sets the trigger level for the failure event. The output from the AC is connected to an RS-latch created by logic gates and inverters as in the actual hardware. The output from the RS-latch is connected to a switch which will break the connection between the PWM signal and the motor, which represents the TCD reacting to a fault event and turning off.
Figure 1. AVR® DB Components
