A single byte (0xFF
) is written into the DFM location. The DFM circuitry
automatically erases the memory location before performing the write operation. If the
DFM address is write-protected, the WR bit will be cleared and the write operation will
not take place.
While erasing/writing data memory, the CPU operation is suspended and resumes when the operation is complete. Upon completion, hardware clears the WR bit, the NVMIF bit is set, and an interrupt will occur if the NVMIE bit is also set.