The MUXPOS bits, the ADC.MUXPOS register, and the REFSEL bits in the ADC.CTRLC register are buffered through a temporary register to which the CPU has random access. This ensures that the channel and reference selections only take place at a safe point during the conversion.
Once the conversion starts, the channel and reference selections are locked to ensure sufficient sampling time for the ADC.
In Single Conversion mode, the channel may be selected before
starting the conversion. The channel selection may be changed one ADC clock
cycle after writing '1' to the STCONV bit.
In Free-Running mode, the channel may be selected before starting the
first conversion. The channel selection may be changed one ADC clock cycle
after writing '1' to the STCONV bit. Since the next
conversion has already started automatically, the next result will reflect
the previous channel selection.