Manage Synthesis Attributes

This feature enables to add or modify the synthesis attributes of the SmartDesign objects (nets, ports, and instances), directly, from the SmartDesign canvas.

Note: Synthesis attributes are not allowed to be configured for the BIF pins, the BIF nets, the Group pins, and the Slices. User defined attributes are not allowed.

The following table lists the synthesis attributes available in the Synopsys^® FPGA synthesis tool that can be added from the SmartDesign.

Table 1. Synthesis Attribute
Attribute	Object
syn_insert_buffer	Port, instance
syn_keep	Net
syn_maxfan	Port, net, instance
syn_no_compile_point	Module or architecture
syn_noclockbuf	Port, net, module or architecture
syn_noprune	Instance, module or architecture
syn_preserve	Port, module or architecture
syn_hier	Module or architecture

Note: For more details for each attribute, refer to Synplify Pro® ME.