SmartDesign is a GUI-driven block-based design entry tool for instantiating, configuring, and connecting various types of design blocks.
The SmartDesign canvas is similar to a canvas, where the components of different types are assembled (instantiated), and connections are made via nets to create a design-rule-checked synthesis-ready HDL file for the complete FPGA design process.
To design with SmartDesign:
- 1.Create a top-level SmartDesign component (analogous to the canvas).
- 2.Add top-level ports.
- 3.Configure/Instantiate components on the top-level SmartDesign.
- 4.Make the connections (analogous to making wire connections to the different components).
- 5.Invoke a DRC on the design.
- 6.Generate the top-level component.