Features

  • Arm Cortex-A7 Core
    • Arm TrustZone®
    • Arm Neon™ multimedia architecture
    • Floating Point Unit
    • Embedded Trace module with instruction trace stream, including 16 Kbytes of CoreSight™ Embedded Trace buffer
    • 32 Kbytes of L1 data cache, 32 Kbytes of L1 instruction cache
    • 256 Kbytes of L2 cache
    • Up to 1-GHz operational frequency
    • Voltage and frequency scaling support
    • 64-bit generic timers
  • Internal Memory Architecture
    • 128 Kbytes of internal SRAM and 5 Kbytes of secure backup RAM
    • 80 Kbytes of maskable ROM, embedding a secure bootloader (boot on QSPI NOR, SLC NAND, SD, e.MMC)
    • 96-Kbyte ROM for NAND Flash ECC tables
    • 40-Kbyte ROM for crypto-libraries (RSA, ECC, etc.)
    • 11-Kbyte internal OTP
  • External Memory Support
    • 16-bit high-bandwidth, double data rate multi-port dynamic RAM controller. Supports up to 16-Gbit 8-bank DDR2/DDR3/DDR3L/LPDDR2/LPDDR3 up to 533 MHz
    • 16-bit static memory controller, FPGA support with synchronous clock
    • 8-bit SLC and MLC NAND controller with up to 32-bit error correcting code
    • One 8-bit high-speed memory card host e.MMC 5.1 (HS400), SD3.0 SDR104 mode support
    • Two 4-bit high-speed memory card hosts e.MMC 4.51 (HS200), SD3.01 SDR104 mode support
    • One octal Serial Peripheral Interface running up to 200-MHz DDR
    • One quad Serial Peripheral Interface
  • System
    • Power-on reset cells, reset controller, shutdown controller, watchdog and secure watchdog timers running on internal slow RC oscillator (32 kHz typical) and real-time clock running on slow crystal oscillator (32.768 kHz)
    • Two internal trimmed RC oscillators with typical values: 32 kHz and 12 MHz
    • Two crystal oscillators: 32.768 kHz and 20 to 50 MHz
    • Eight PLLs for core, system bus and peripherals, serial interfaces, DDR I/Os, pixel clock, audio, USB, MIPI CSI-2 and Ethernet
    • Two 32-channel DMA with per-channel security configuration
    • One 8-channel DMA dedicated to memory-to-memory transactions
    • Eight programmable clock output signals
  • Power Considerations
    • Different power domains and power modes to reduce power consumption
    • Low-power consumption in Backup mode with 5 Kbytes of secure backup SRAM and DDR-SDRAM in Self-Refresh mode
    • Low-power with SRAM and register retention, wake-up from various events (USB, CAN, Ethernet WOL, FLEXCOMs), internal events (RTC, timer) and I/O activity
    • Embedded LDOs for MIPI CSI-2, analog and PLLs, to enable low-cost power management solutions
    • Optimum connection to Microchip MCP16501/2 PMICs to enter and exit various power modes of the application
  • Multimedia Peripherals
    • Audio
      • Two synchronous serial controllers, each with 16 channels of up to 32-bit TDM data
      • One inter-IC sound multi-channel controller with TDM256 support
      • Up to two 4-channel pulse density microphone controllers; support for eight microphones in parallel
      • One Sony/Philips digital interface transmitter and receiver
      • Audio sample rate converter including four stereo channels
    • Image
      • Image sensor controller, ITU-R BT. 601/656 supporting up to eight megapixels for still images and 60 fps in 720p mode, 8 bits, raw Bayer, YCbCr, monochrome, camera ISP
      • 2-lane MIPI CSI-2 (D-PHY) and 12-bit RGB interface support
  • Peripherals
    • Two high-speed USB devices and three high-speed USB hosts sharing three on-chip transceivers
    • One 10/100/1000 Gigabit Ethernet MAC supporting RGMII, MII and RMII (GMAC0) and one 10/100 Ethernet MAC supporting MII and RMII (GMAC1) compliant with:
      • IEEE802.3az Energy-Efficient Ethernet
      • IEEE802.1AS Timestamping for Ethernet AVB support
      • IEEE802.1Qav Credit-based traffic shaping hardware support
      • IEEE1588 Precision Time Protocol
      • IEEE1588 Timestamp Unit (TSU) with TSU timer comparison signal triggering a timer counter and available on a PIO line
    • Six flexible data rate CAN-FD controllers with SRAM-based mailboxes with time- and event-triggered transmission
    • Twelve FLEXCOMs (USART, SPI and TWIHS)
    • Six 64-bit timers
    • Two three-channel 32-bit timer counters, with PWM generation
    • One four-channel 16-bit PWM controller
    • One 19-channel 12-bit analog-to-digital converter, up to 1 Msps
  • Safety
    • Temperature and core voltage monitoring
    • Zero-power power-on reset cells
    • Main crystal monitor and clock failure detector with failsafe switchover to main RC oscillator
    • 32 kHz crystal monitor and clock failure detector with failsafe switchover to internal 32 kHz RC oscillator
    • Integrity check monitor based on SHA256
    • Safety critical modules (WDT, RSTC, SHDWC, etc.) running on always-on slow RC oscillator
    • Register write protection
  • Security
    • TrustZone support
    • One Secure TrustZone watchdog timer running on RC oscillator, providing protection against TrustZone starvation
    • Temperature, voltage and frequency monitoring
    • Secure backup SRAM
      • 5 Kbytes scrambled with non-imprinting support powered with VBAT or VDDIN33:
        • 1 Kbyte non erasable on tamper detection
        • 4 Kbytes erasable on tamper detection
    • Four tamper pins for static or dynamic detection
      • Can be used as regular wake-up lines
    • 256-bit general purpose backup register, erasable on tamper detection
    • Programmable OTP with bits available for user purposes
    • Configurable JTAG security (full debug, non-secure-only debug, no debug)
    • 128-bit AES on-the-fly encryption/decryption on DDR memory, SMC, QSPI0 and QSPI1, including automatic key load at start-up. Separate keys for secure and non-secure accesses (TZAESB).
    • True random number generator compliant with NIST Special Publication 800-22 Tests Suite and FIPS PUB 140-2 and 140-3
    • Secure RTC
  • Cryptography
    • SHA (SHA1, SHA224, SHA256, SHA384, SHA512) compliant with FIPS Publications 180-2
    • AES: 256-, 192-, 128-bit key algorithm, compliant with FIPS PUB 197 specifications
    • TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3 specifications
    • Public Key Coprocessor (CPKCC) and associated Classical Public Key Cryptography Library (CPKCL) for RSA, DSA, ECC GF(2n), ECC GF(p)
  • Up to 136 I/Os
    • Fully programmable through set/clear registers
    • Multiplexing of eight peripheral functions per I/O line
    • Each I/O line can be assigned to a peripheral or used as a general purpose I/O
    • Synchronous output, possibility to set or clear simultaneously up to 32 I/O lines in a single write
    • General purpose analog and digital inputs tolerant to positive and negative current injection
  • Design for Low ElectroMagnetic Interference (EMI)
    • Slewrate-controlled I/Os
    • DDR PHY with impedance-calibrated drivers
    • Spread spectrum PLLs
    • Careful BGA power/ground ball assignment to provide optimum decoupling capacitors placement
  • Microchip Recommended Power Management Integrated Circuits (PMICs)
    • MCP16502, 6-channel PMIC with I²C control interface; supports dynamic voltage scaling and processor Low-Power modes (ULP2, BSR)
    • MCP16501, 4-channel PMIC optimized for compact PCB layout; supports processor Low-Power mode (BSR)
  • Junction Temperature (TJ) Range
    • Industrial: -40°C to +105°C
    • Automotive: -40°C to +125°C
  • Automotive Qualification
    • AEC-Q100 Grade 2 qualified using the following mission profile:
      • 20 khrs of operation with junction temperature usage as -40°C = 6% of lifetime, 70°C = 25%, 85°C = 25%, 100°C = 25%, 115°C = 14%, 125°C = 5%
      • Maximum CPU speed = 800 MHz
    • ESD-CDM classification level C2
    • AEC-Q006 set of tests applies as only copper wire interconnections are used
  • Package
    • 14x14 mm², 0.65 mm pitch, 343-ball TFBGA, optimized for standard class PCB layout (down to four layers)