26.11 Register Summary - Timer2


Offset	Name	Bit Pos.	7	6	5	4	3
0x00 ... 0x0321	Reserved
0x0322	T2TMR	7:0	T2TMR[7:0]
0x0323	T2PR	7:0	T2PR[7:0]
0x0324	T2CON	7:0	ON	CKPS[2:0]			OUTPS[3:0]
0x0325	T2HLT	7:0	PSYNC	CPOL	CSYNC	MODE[4:0]
0x0326	T2CLKCON	7:0				CS[4:0]
0x0327	T2RST	7:0			RSEL[5:0]
0x0328 ... 0x032D	Reserved
0x032E	T4TMR	7:0	T4TMR[7:0]
0x032F	T4PR	7:0	T4PR[7:0]
0x0330	T4CON	7:0	ON	CKPS[2:0]			OUTPS[3:0]
0x0331	T4HLT	7:0	PSYNC	CPOL	CSYNC	MODE[4:0]
0x0332	T4CLKCON	7:0				CS[4:0]
0x0333	T4RST	7:0			RSEL[5:0]
0x0334 ... 0x0339	Reserved
0x033A	T6TMR	7:0	T6TMR[7:0]
0x033B	T6PR	7:0	T6PR[7:0]
0x033C	T6CON	7:0	ON	CKPS[2:0]			OUTPS[3:0]
0x033D	T6HLT	7:0	PSYNC	CPOL	CSYNC	MODE[4:0]
0x033E	T6CLKCON	7:0				CS[4:0]
0x033F	T6RST	7:0			RSEL[5:0]