5.1 Operation

To use the high priority vector feature, simply write the desired interrupt vector address to the CPUINT.LVL1VEC register and this interrupt will be assigned level 1 priority. This feature is disabled when the register value is 0x00. Refer to the device datasheet for the interrupt vector mapping.

If interrupted by the level 1 interrupt, the level 0 handler will resume execution when the level 1 handler is done. It is important to make sure a level 1 interrupt will not interfere with the execution of any time critical level 0 interrupts. The LVL0EX bit in the CPUINT.STATUS register can be read to check if the level 1 interrupt has interrupted an executing level 0 ISR.