Introduction

One of the challenges that digital designers frequently run into involves getting rid of glitches in their design. This is typically accounted for by ensuring there is adequate set-up and hold time when data is latched.

A glitch is a signal which does not remain active for a full clock period. If a signal with a glitch feeds the clock line of numerous latches, some of the latches may be updated while others may not. This situation is clearly one that designers want to avoid.

It should also be noted that propagation delay varies with temperature, therefore, a design which does not produce glitches during development may produce glitches under different conditions.

The Configurable Logic Cell (CLC) is one of the Core Independent Peripherals (CIPs) that Microchip Technology offers in its 8 and 16-bit microcontrollers. It can be used to develop a custom circuit that can help interface external glitch-prone signals to the PIC® controller. This document explains the general technique and shows its implementation using Microchip’s MPLAB® Code Configurator Melody.