6 Hardware Interface for Memory Programming

For memory programming, the minimum set of hardware connections required to interface an external host MCU to the BM70/71 module (see the following figure). After making these hardware connections between the host MCU and the BM70/71 module, the BM70/71 module allows the host MCU to control the behavior of the following:
  • To enter Memory Programming mode
  • To enter Test mode
  • Communicate
  • Calibrate
Figure 6-1. Hardware Interface Necessary for Memory Programming

The level of a hardware pin P2_0 determines the operation or mode of the BM70/71 module. The user must sample the pin when the RST_N pin goes active. The RST_N signal must be active for a minimum time to ensure the pin P2_0 logic level is latched into the IC correctly. When the BM70/71 module enters the applicable mode, communication over the UART interface becomes active. The data or protocol used to communicate between the host MCU and the BM70/71 module is based on the mode the BM70/71 module enters after a reset.

The programming modes of the BM70/71 module are as follows:
  • Memory Programming mode – Pin P2_0 is latched by the BM70/71 module to a logic level ‘0’.
  • Application or Run mode (where general Bluetooth Low Energy operation is available) – Pin P2_0 is latched by the BM70/71 module to a logic level ‘1’. For more details on Run/Application mode, refer to the BM70/71 Bluetooth® Low Energy Module User’s Guide (DS50002542).
The following table summarizes the use of the P2_0 pin and the following figures illustrate the signal level and timing control of pin P2_0 by a host MCU during a Reset or Power-on Reset (POR) event.
Table 6-1. Summary of Modes available based on Pin P2_0
P2_0 Logic LevelModeProtocols Enabled
0-Low
  • Memory Programming
  • Test
  • HCI commands
  • HCI-ISDAP commands
1-HighApplication or RunBM70 command set

The preceding table provides details about the two protocols and two modes available, when the pin P2_0 is at logic level of ‘0’. The header value and the data payload of the protocol packet determine what type of mode/protocol the host MCU is setting the BM70/71 module into.

The following figure and the Figure 6-3 illustrates the timing diagram for P2_0 pin with respect to the Reset pin and the input voltage pin respectively.
Figure 6-2. Timing Diagram for Pin P2_0 with Respect to Reset Pin
Figure 6-3. Timing Diagram for Pin P2_0 with Respect to Input Voltage