Introduction

The PIC18F26/46/56Q43 devices you have received conform functionally to the current device data sheet (DS40002171F), except for the anomalies described in this document.

The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in the table below.

The errata described in this document will be addressed in future revisions of the PIC18F26/46/56Q43 silicon.

Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current.
Table . Silicon Device Identification
Part Number Device IDRevision ID
B0B2B3F1G1
PIC18F26Q430x74200xA0400xA0420xA0430xA1410xA181
PIC18F46Q430x74400xA0400xA0420xA0430xA1410xA181
PIC18F56Q430x74600xA0400xA0420xA0430xA1410xA181
Important: Refer to the Device/Revision ID section in the current “PIC18FXXQ43 Family Programming Specification” (DS40002079) for more detailed information on Device Identification and Revision IDs for your specific device.
Table . Silicon Issue Summary
ModuleFeatureItem No.Issue SummaryAffected Revisions
B0B2B3F1G1
ADCCCapacitive Voltage DividerCapacitive Voltage Divider (CVD)CVD is only functional on PORTA[2:0] and PORTB[4:0]X
Double Sample ConversionsDouble Sample ConversionsAn unexpected acquisition time is added between the first and second conversions.XXXXX
OscillatorXT modeMaximum Clock Frequency Limited to 2 MHz for XT ModeMaximum clock frequency limited to 2 MHz for XT modeXX
I2CI2CThe I2CxADR0/1/2/3 Registers Have Incorrect Reset ValueI2CxADR0/1/2/3 registers have incorrect Reset valueXXX
I2CThe I2C Start and/or Stop Flags May Be Set When I2C Is EnabledI2C Start and/or Stop flags may be set when I2C is enabledXXXX
I2CMDR Bit Is Not Cleared after Bus Time-OutMDR bit is not cleared after Bus TimeoutXXXXX
I2CBus Time-Out Not Detected Properly When External Host Clock StretchesBus Timeout not Detected Properly when External Host Clock StretchesXXXXX
Clock Stretch DisableClock Stretch Disable Not Working ProperlyClock Stretch Disable not working properlyXXXXX
I2CBus Time-Out Causes False Start/StopBus Timeout causes False Start/StopXXXXX
Multi-Host modeOperating in Multi-Host Mode Will Cause Bus FailuresMulti-Master Mode will cause bus failuresXXXXX
Bus Free TimeThe Bus Free Divider Ratio BFREDR = 1 Value Is Not FunctionalI2C - The Bus Free Divider Ratio BFREDR = 1 value is not functionalXXXXX
I2CCSTR Bit Is Not Cleared after Bus Time-OutCSTR bit is not cleared after Bus TimeoutXXXXX
Bus CollisionBus Collision Followed by a Stop Condition during a Transaction by an External Host Device May Hang the BusBus Collision Followed By a Stop Condition During a Transaction by an External Host Device May Hang the BusXXXXX
Multi-Host ArbitrationI2C Module May Hang the Bus during Multi-Host ArbitrationI2C Module May Hang the Bus During Multi-Host ArbitrationXXXXX
SRAMSRAM read-backSRAM Read-BackSRAM read-back can be incorrectX
In-Circuit DebugSoftware breakpointsSoftware Breakpoints Are Not AvailableSoftware breakpoints are not availableXXXXX
SMTReset BitReset BitModule stops working if RST bit is set while prescaler setting is not zeroXXXXX
Universal Asynchronous Receiver TransmitterUARTUART TXDE Signal May Go Low before the STOP Bit Has Been Entirely TransmittedUART TXDE signal may go low before the STOP bit has been entirely transmittedXXXXX
Note: Only those issues indicated in the last column apply to the current silicon revision.