Introduction

The PIC18F26/46/56Q43 devices you have received conform functionally to the current device data sheet (DS40002171F), except for the anomalies described in this document.

The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in the table below.

The errata described in this document will be addressed in future revisions of the PIC18F26/46/56Q43 silicon.

Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current.

Table . Silicon Device Identification
Part Number	Device ID	Revision ID
Part Number	Device ID	B0	B2	B3	F1	G1
PIC18F26Q43	0x7420	0xA040	0xA042	0xA043	0xA141	0xA181
PIC18F46Q43	0x7440	0xA040	0xA042	0xA043	0xA141	0xA181
PIC18F56Q43	0x7460	0xA040	0xA042	0xA043	0xA141	0xA181

Important: Refer to the Device/Revision ID section in the current “PIC18FXXQ43 Family Programming Specification” (DS40002079) for more detailed information on Device Identification and Revision IDs for your specific device.

Table . Silicon Issue Summary
Module	Feature	Item No.	Issue Summary	Affected Revisions
Module	Feature	Item No.	Issue Summary	B0	B2	B3	F1	G1
ADCC	Capacitive Voltage Divider	Capacitive Voltage Divider (CVD)	CVD is only functional on PORTA[2:0] and PORTB[4:0]	X
ADCC	Double Sample Conversions	Double Sample Conversions	An unexpected acquisition time is added between the first and second conversions.	X	X	X	X	X
Oscillator	XT mode	Maximum Clock Frequency Limited to 2 MHz for XT Mode	Maximum clock frequency limited to 2 MHz for XT mode	X	X
I²C	I²C	The I2CxADR0/1/2/3 Registers Have Incorrect Reset Value	I2CxADR0/1/2/3 registers have incorrect Reset value	X	X	X
	I²C	The I²C Start and/or Stop Flags May Be Set When I²C Is Enabled	I2C Start and/or Stop flags may be set when I2C is enabled	X	X	X	X
	I²C	MDR Bit Is Not Cleared after Bus Time-Out	MDR bit is not cleared after Bus Timeout	X	X	X	X	X
	I²C	Bus Time-Out Not Detected Properly When External Host Clock Stretches	Bus Timeout not Detected Properly when External Host Clock Stretches	X	X	X	X	X
	Clock Stretch Disable	Clock Stretch Disable Not Working Properly	Clock Stretch Disable not working properly	X	X	X	X	X
	I²C	Bus Time-Out Causes False Start/Stop	Bus Timeout causes False Start/Stop	X	X	X	X	X
	Multi-Host mode	Operating in Multi-Host Mode Will Cause Bus Failures	Multi-Master Mode will cause bus failures	X	X	X	X	X
	Bus Free Time	The Bus Free Divider Ratio BFREDR = 1 Value Is Not Functional	I2C - The Bus Free Divider Ratio BFREDR = 1 value is not functional	X	X	X	X	X
	I²C	CSTR Bit Is Not Cleared after Bus Time-Out	CSTR bit is not cleared after Bus Timeout	X	X	X	X	X
	Bus Collision	Bus Collision Followed by a Stop Condition during a Transaction by an External Host Device May Hang the Bus	Bus Collision Followed By a Stop Condition During a Transaction by an External Host Device May Hang the Bus	X	X	X	X	X
	Multi-Host Arbitration	I²C Module May Hang the Bus during Multi-Host Arbitration	I2C Module May Hang the Bus During Multi-Host Arbitration	X	X	X	X	X
SRAM	SRAM read-back	SRAM Read-Back	SRAM read-back can be incorrect	X
In-Circuit Debug	Software breakpoints	Software Breakpoints Are Not Available	Software breakpoints are not available	X	X	X	X	X
SMT	Reset Bit	Reset Bit	Module stops working if RST bit is set while prescaler setting is not zero	X	X	X	X	X
Universal Asynchronous Receiver Transmitter	UART	UART TXDE Signal May Go Low before the STOP Bit Has Been Entirely Transmitted	UART TXDE signal may go low before the STOP bit has been entirely transmitted	X	X	X	X	X
Note: Only those issues indicated in the last column apply to the current silicon revision.