40.5 I/O Pins

Figure 40-63. Fall Time vs. VDD (PORTCTRL.SRL = 0x00)
Figure 40-64. Fall Time vs. VDD (PORTCTRL.SRL = 0x01)
Figure 40-65. Rise Time vs. VDD (PORTCTRL.SRL = 0x00)
Figure 40-66. Rise Time vs. VDD (PORTCTRL.SRL = 0x01)
Figure 40-67. Input Pin with Schmitt Trigger - Maximum VIL vs. VDD
Figure 40-68. Input Pin with Schmitt Trigger - Minimum VIH vs. VDD
Figure 40-69. Input Pin with Schmitt Trigger - Hysteresis vs. VDD
Figure 40-70. Input Pin with I2C Trigger - Maximum VIL vs. VDD
Figure 40-71. Input Pin with I2C Trigger - Minimum VIH vs. VDD
Figure 40-72. Input Pin SMBus - Maximum VIL vs. VDD
Figure 40-73. Input Pin SMBus - Minimum VIH vs. VDD
Figure 40-74. Reset Pin VIL vs. VDD
Figure 40-75. Reset Pin VIH vs. VDD
Figure 40-76. Weak Pull-Up Current vs. VDD
Figure 40-77. Output Pin - Maximum VOL vs. Current, VDD = 1.8V
Figure 40-78. Output Pin - Minimum VOH vs. Current, VDD = 1.8V
Figure 40-79. Output Pin - Maximum VOL vs. Current, VDD = 3.0V
Figure 40-80. Output Pin - Minimum VOH vs. Current, VDD = 3.0V
Figure 40-81. Output Pin - Maximum VOL vs. Current, VDD = 5.5V
Figure 40-82. Output Pin - Minimum VOH vs. Current, VDD = 5.5V