6 Slave Mode
| Setting | Description |
|---|---|
TXR = 1 | Data from the TX buffer is transmitted and the write FIFO pointer is incremented. If the TX buffer is empty, the most recently received data is transmitted and the Transmit Underflow Interrupt Flag (TXUIF) bit is set to indicate that this type of error occurred. |
TXR = 0 | Data in the TX buffer is transmitted if available, but the write FIFO pointer is not incremented. If the TX buffer is empty, the most recently received data is transmitted, but the TXUIF bit will not be set. |
RXR = 1 | Data will be stored in the RX buffer if it is not full and the read FIFO pointer is incremented. If data is received and the RX buffer is full, the Receive Overflow Interrupt Flag (RXOIF) bit is set to indicate the error and the data received is discarded. |
RXR = 0 | All received data will be ignored and not stored in the RX register. |
The TXR and RXR bits control how data is transferred when a device is configured as a slave on the SPI bus. Table 6-1 summarizes how the configuration of the RXR and TXR bits affect the operation of the SPI module while in Slave mode. For more information about how data is transmitted/received while in Slave mode, refer to the device data sheet.
In the event where the Slave Select (SS) line transitions to an inactive state while a data transfer is ongoing, the Slave Select Fault (SSFLT) bit in the SPIxCON2 register will be set. The SSP bit of the SPIxCON1 register controls slave select polarity. When the SSP bit is set, the Slave Select (SS) line is active-low. Conversely, when the SSP bit is cleared, the Slave Select (SS) line is active-high. In addition to this, the SCK pin must always be an input and configured to the same clock polarity and edge as the master device. Clock polarity is controlled by the CKP bit and the clock edge is set by the CKE bit both found in the SPIxCON1 register.