2 Configuration of the SPI Peripheral

Operation of the SPI module is controlled by the following registers:
  • SPIxCON0: Used to enable/disable the SPI module, select LSb or MSb first data exchange, specify whether the device is a master or slave, and contains the bit length mode select bit (BMODE)
  • SPIxCON1: Used to configure the polarity of the SS, SDI, SDO, SDK lines, enable fast start, select leading clock edge on CKE, and set the sample phase control bit.
  • SPIxCON2: Used to configure slave select settings, and contains the TXR and RXR control bits.
  • SPIxTWIDTH: SPI Transfer Width Register
  • SPIxBAUD: SPI Baud Rate Generator Control Register
  • SPIxINTE: Interrupt Enable Register
  • SPIxINTF: Interrupt Flag Register
  • SPIxTCTH/L: SPI Transfer Counter Register Pair
  • SPIxSTATUS: FIFO Status Register
  • SPIxRxB: Receive Buffer Register
  • SPIxTxB: Transmit Buffer Register
  • SPIxCLK: Clock Source Selection Register
Table 2-1. Registers Associated with SPI
NameBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
SPIxINTFSRMTIFTCZIFSOSIFEOSIF-RXOIFTXUIF-
SPIxINTESRMTIETCZIESOSIEEOSIE-RXOIETXUIE-
SPIxTCNTH-----TCNT10TCNT9TCNT8
SPIxTCNTLTCNT7TCNT6TCNT5TCNT4TCNT3TCNT2TCNT1TCNT0
SPIxTWIDTH-----TWIDTH2TWIDTH1TWIDTH0
SPIxBAUDBAUD7BAUD6BAUD5BAUD4BAUD3BAUD2BAUD1BAUD0
SPIxCON0EN----LSBFMSTBMODE
SPIxCON1SMPCKECKPFST-SSOSDIPSDOP
SPIxCON2BUSYSSFLT---SSETTXRRXR
SPIxSTATUSTXWE-TXBE-RXRECLRBF-RXBF
SPIxRXBRXB7RXB6RXB5RXB4RXB3RXB2RXB1RXB0
SPIxTXBTXB7TXB6TXB5TXB4TXB3TXB2TXB1TXB0
SPIxCLK----CLK3CLK2CLK1CLK0
Table 2-2. Registers Associated with IO Control
NameBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
SPIxSCKPPS---SPIxSCKPPS4SPIxSCKPPS3SPIxSCKPPS2SPIxSCKPPS1SPIxSCKPPS0
SPIxSSPPS---SPIxSSPPS4SPIxSSPPS3SPIxSSPPS2SPIxSSPPS1SPIxSSPPS0
SPIxSDIPPS---SPIxSDIPPS4SPIxSDIPPS3SPIxSDIPPS2SPIxSDIPPS1SPIxSDIPPS0