5 Using the SPI with DMA

This SPI module has separate receive and transmit FIFO buffers that both allow for Direct Memory Access (DMA) bus connections. This can be useful in certain applications where data transfers need to be made without CPU intervention. The SPI is capable of triggering interrupts under several different conditions. The three top-level SPI interrupts, SPI Transmit, SPI Receive and SPI Module Status, can be found in the device's PIR registers

The DMA module can be used to implement fully interrupt driven operation with the SPI module. Instead of loading and clearing the TXFIFO and RXFIFO in software, the DMA can be configured to perform these tasks when certain triggers occur. The system arbitration decides memory access allocation, depending on priority and can be configured to give the DMA priority over the CPU. In the default case where the CPU has top priority, the DMA will wait for unused CPU cycles to perform DMA transfers. When the DMA is given top priority, the CPU will be stalled until the DMA has completed its transfers. The example below demonstrates how the system arbiter can be used to give the DMA top priority.

// System Arbiter Configuration
ISRPR = 0x01; // Interrupt Service Routine Priority;
MAINPR = 0x02; // Main Routine Priority;
DMA1PR = 0x00; // DMA1 Priority;
DMA2PR = 0x03; // DMA2 Priority;
SCANPR = 0x04; // Scanner Priority;
asm (”BCF INTCON0, 7”); // disable Global Interrupts
asm (”BANKSEL PRLOCK”); 
asm (”MOVLW 0x55”); 
asm (”MOVWF PRLOCK”); // Arbiter Priority lock 
asm (”MOVLW 0XAA”); 
asm (”MOVWF PRLOCK”); 
asm (”BSF PRLOCK, 0”); 
asm (”BSF INTCON0, 7”); // enable Global Interrupts