Introduction

The PIC18F26/45/46/55/56Q24 devices that you have received conform functionally to the current device data sheet (DS40002503C), except for the anomalies described in this document.

The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in the table below.

The errata described in this document will be addressed in future revisions of the PIC18F26/45/46/55/56Q24 silicon.

Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current.

Table . Silicon Device Identification
Part Number	Device ID	Revision ID
Part Number	Device ID	A1	A3
PIC18F26Q24	0x78E0	0xA001	0xA003
PIC18F45Q24	0x7940	0xA001	0xA003
PIC18F46Q24	0x7900	0xA001	0xA003
PIC18F55Q24	0x7960	0xA001	0xA003
PIC18F56Q24	0x7920	0xA001	0xA003

Important: Refer to the Device/Revision ID section in the current “PIC18-Q24 Family Programming Specification” (DS40002414) for more detailed information on Device Identification and Revision IDs for your specific device.

Table . Silicon Issue Summary
Module	Feature	Item No.	Issue Summary	Affected Revisions
Module	Feature	Item No.	Issue Summary	A1	A3
Universal Timer Module	Level-Triggered ERS Start/Reset condition	Dead Zone Exists in Level-Triggered Start/Reset Condition When an ERS Signal Is Generated Due to an SFR Access	Dead zone exists in level-triggered Start/Reset condition when ERS signal is generated due to an SFR access	X	X
Universal Timer Module	Interrupts	Interrupts Do Not Work When Leaving Debug Mode	Interrupts do not work when leaving Debug mode	X	X
Multi-Voltage I/O	V_DDIOx I/O Monitor Disable	V_DDIOx I/O Monitor Disable Feature Causes Adverse MVIO Module Behavior	V_DDIOx I/O Monitor Disable feature causes adverse MVIO module behavior	X
Multi-Voltage I/O	MVIO Low-Voltage Detect output status bit	V_DDIOx Low-Voltage Detect Status Bit (LVDSTAT) Does Not Return LVD Status	V_DDIOx Low-Voltage Detect Status bit does not return LVD status	X
I²C	Bus Time-Out	MDR Bit Is Not Cleared after Bus Time-Out	MDR bit is not cleared after Bus Time-Out	X
	Bus Time-Out	Bus Time-Out Not Detected Properly When External Host Clock Stretches	Bus Time-Out not detected properly when External Host Clock stretches	X
	Clock Stretch Disable	Clock Stretch Disable Not Working Properly	Clock Stretch Disable not working properly	X
	Bus Time-Out	Bus Time-Out Causes False Start/Stop	Bus Time-Out causes false Start/Stop	X
	Multi-Host Mode	Operating in Multi-Host Mode Will Cause Bus Failures	Multi-Host Mode will cause Bus failures	X	X
	Bus Time-Out	CSTR Bit Is Not Cleared after Bus Time-Out	CSTR bit is not cleared after Bus Time-Out	X
	Bus Collision	Bus Collision Followed by a Stop Condition During a Transaction by an External Host Device May Hang the Bus	Bus Collision followed by a Stop during a transaction by an external Host device may hang the bus	X	X
	Bus Free Time	The Bus Free Divider Ratio BFREDR = 1 Value Is Not Functional	The Bus Free Divider Ratio BFREDR = 1 value is not functional	X
	Multi-Host Mode	I²C Module May Hang the Bus During Multi-Host Arbitration	Module may hang the I²C bus during Multi-Host arbitration	X	X
Oscillator	Secondary Oscillator (SOSC)	SOSC Does Not Function When the Device Is Configured to Run From an External Oscillator	SOSC does not function when the device is configured to run from an external oscillator	X
Comparator	Ultra-Low Power (ULP) Operation	Comparator Module Will Not Function in ULP Mode	Comparator module will not function in ULP mode	X
Timer1	Timer1 Gate Source	Changing the Timer1 Gate Source May Cause Unexpected Interrupts	Changing the Timer1 Gate Source May Cause Unexpected Interrupts	X
Note: Only those issues indicated in the last column apply to the current silicon revision.