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AVR® Instruction Set Manual
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6
Instruction Description
6.39
CLR – Clear Register
Introduction
1
Instruction Set Nomenclature
2
CPU Registers Located in the I/O Space
3
The Program and Data Addressing Modes
4
Conditional Branch Summary
5
Instruction Set Summary
6
Instruction Description
6.1
ADC – Add with Carry
6.2
ADD – Add without Carry
6.3
ADIW – Add Immediate to Word
6.4
AND – Logical AND
6.5
ANDI – Logical AND with Immediate
6.6
ASR – Arithmetic Shift Right
6.7
BCLR – Bit Clear in SREG
6.8
BLD – Bit Load from the T Bit in SREG to a Bit in Register
6.9
BRBC – Branch if Bit in SREG is Cleared
6.10
BRBS – Branch if Bit in SREG is Set
6.11
BRCC – Branch if Carry Cleared
6.12
BRCS – Branch if Carry Set
6.13
BREAK – Break
6.14
BREQ – Branch if Equal
6.15
BRGE – Branch if Greater or Equal (Signed)
6.16
BRHC – Branch if Half Carry Flag is Cleared
6.17
BRHS – Branch if Half Carry Flag is Set
6.18
BRID – Branch if Global Interrupt is Disabled
6.19
BRIE – Branch if Global Interrupt is Enabled
6.20
BRLO – Branch if Lower (Unsigned)
6.21
BRLT – Branch if Less Than (Signed)
6.22
BRMI – Branch if Minus
6.23
BRNE – Branch if Not Equal
6.24
BRPL – Branch if Plus
6.25
BRSH – Branch if Same or Higher (Unsigned)
6.26
BRTC – Branch if the T Bit is Cleared
6.27
BRTS – Branch if the T Bit is Set
6.28
BRVC – Branch if Overflow Cleared
6.29
BRVS – Branch if Overflow Set
6.30
BSET – Bit Set in SREG
6.31
BST – Bit Store from Bit in Register to T Bit in SREG
6.32
CALL – Long Call to a Subroutine
6.33
CBI – Clear Bit in I/O Register
6.34
CBR – Clear Bits in Register
6.35
CLC – Clear Carry Flag
6.36
CLH – Clear Half Carry Flag
6.37
CLI – Clear Global Interrupt Enable Bit
6.38
CLN – Clear Negative Flag
6.39
CLR – Clear Register
6.39.1
Description
6.39.2
Status Register (SREG) and Boolean Formula
6.40
CLS – Clear Sign Flag
6.41
CLT – Clear T Bit
6.42
CLV – Clear Overflow Flag
6.43
CLZ – Clear Zero Flag
6.44
COM – One’s Complement
6.45
CP – Compare
6.46
CPC – Compare with Carry
6.47
CPI – Compare with Immediate
6.48
CPSE – Compare Skip if Equal
6.49
DEC – Decrement
6.50
DES – Data Encryption Standard
6.51
EICALL – Extended Indirect Call to Subroutine
6.52
EIJMP – Extended Indirect Jump
6.53
ELPM – Extended Load Program Memory
6.54
EOR – Exclusive OR
6.55
FMUL – Fractional Multiply Unsigned
6.56
FMULS – Fractional Multiply Signed
6.57
FMULSU – Fractional Multiply Signed with Unsigned
6.58
ICALL – Indirect Call to Subroutine
6.59
IJMP – Indirect Jump
6.60
IN - Load an I/O Location to Register
6.61
INC – Increment
6.62
JMP – Jump
6.63
LAC – Load and Clear
6.64
LAS – Load and Set
6.65
LAT – Load and Toggle
6.66
LD – Load Indirect from Data Space to Register using X
6.67
LD (LDD) – Load Indirect from Data Space to Register using Y
6.68
LD (LDD) – Load Indirect From Data Space to Register using Z
6.69
LDI – Load Immediate
6.70
LDS – Load Direct from Data Space
6.71
LDS (AVRrc) – Load Direct from Data Space
6.72
LPM – Load Program Memory
6.73
LSL – Logical Shift Left
6.74
LSR – Logical Shift Right
6.75
MOV – Copy Register
6.76
MOVW – Copy Register Word
6.77
MUL – Multiply Unsigned
6.78
MULS – Multiply Signed
6.79
MULSU – Multiply Signed with Unsigned
6.80
NEG – Two’s Complement
6.81
NOP – No Operation
6.82
OR – Logical OR
6.83
ORI – Logical OR with Immediate
6.84
OUT – Store Register to I/O Location
6.85
POP – Pop Register from Stack
6.86
PUSH – Push Register on Stack
6.87
RCALL – Relative Call to Subroutine
6.88
RET – Return from Subroutine
6.89
RETI – Return from Interrupt
6.90
RJMP – Relative Jump
6.91
ROL – Rotate Left trough Carry
6.92
ROR – Rotate Right through Carry
6.93
SBC – Subtract with Carry
6.94
SBCI – Subtract Immediate with Carry SBI – Set Bit in I/O Register
6.95
SBI – Set Bit in I/O Register
6.96
SBIC – Skip if Bit in I/O Register is Cleared
6.97
SBIS – Skip if Bit in I/O Register is Set
6.98
SBIW – Subtract Immediate from Word
6.99
SBR – Set Bits in Register
6.100
SBRC – Skip if Bit in Register is Cleared
6.101
SBRS – Skip if Bit in Register is Set
6.102
SEC – Set Carry Flag
6.103
SEH – Set Half Carry Flag
6.104
SEI – Set Global Interrupt Enable Bit
6.105
SEN – Set Negative Flag
6.106
SER – Set all Bits in Register
6.107
SES – Set Sign Flag
6.108
SET – Set T Bit
6.109
SEV – Set Overflow Flag
6.110
SEZ – Set Zero Flag
6.111
SLEEP
6.112
SPM (AVRe) – Store Program Memory
6.113
SPM (AVRxm, AVRxt) – Store Program Memory
6.114
ST – Store Indirect From Register to Data Space using Index X
6.115
ST (STD) – Store Indirect From Register to Data Space using Index Y
6.116
ST (STD) – Store Indirect From Register to Data Space using Index Z
6.117
STS – Store Direct to Data Space
6.118
STS (AVRrc) – Store Direct to Data Space
6.119
SUB – Subtract Without Carry
6.120
SUBI – Subtract Immediate
6.121
SWAP – Swap Nibbles
6.122
TST – Test for Zero or Minus
6.123
WDR – Watchdog Reset
6.124
XCH – Exchange
7
Appendix A Device Core Overview
8
Revision History
Legal Disclaimer
Microchip Information
6.39 CLR – Clear Register
