23.4.2 MVIO Status Register

Note:
  1. This bit will always read back as '0' when the VDDIOx Low-Voltage detection is disabled (LVD = 0b000), and when the the VDDIOx voltage domain is not ready for use.
  2. When the LVDEN bit is disabled or when the LVD[3:0] bits are clear (LVD[3:0] == 'b0000), the associated system level interrupts (VDDIOxLVDRIF and VDDIOxLVDFIF) will no longer operate and should be disabled using the respective interrupt enable bit (VDDIOxLVDRIE and VDDIOxLVDFIE). The system level interrupts will operate when the LVDEN bit is enabled and the LVD[3:0] bits have a non-zero value (LVD[3:0] != 'b0000).
Name: VDDIOxSTAT
Offset: 0x010E

Bit 76543210 
  LVDSTATRDY      
Access RR 
Reset 00 

Bit 6 – LVDSTAT VDDIOx Low Voltage Detect Output(1)

ValueDescription
1 VDDIOx voltage is below the selected detection limit (LVD)
0 VDDIOx voltage is above the selected detection limit (LVD)

Bit 5 – RDY VDDIOx Ready Status Flag

ValueDescription
1 VDDIOx supply is within an acceptable range and this voltage domain is ready to use
0 VDDIOx supply is not within an acceptable range and this voltage domain is not ready to use
This bit will always read back as '0' when the VDDIOx Low-Voltage detection is disabled (LVD = 0b000), and when the the VDDIOx voltage domain is not ready for use. When the LVDEN bit is disabled or when the LVD[3:0] bits are clear (LVD[3:0] == 'b0000), the associated system level interrupts (VDDIOxLVDRIF and VDDIOxLVDFIF) will no longer operate and should be disabled using the respective interrupt enable bit (VDDIOxLVDRIE and VDDIOxLVDFIE). The system level interrupts will operate when the LVDEN bit is enabled and the LVD[3:0] bits have a non-zero value (LVD[3:0] != 'b0000).