23.4.1 MVIO Control Register

Note:
  1. Refer to the MVIO VDDIOx Low-Voltage Detect parameters in the "Electrical Specifications" chapter for more information.
  2. When the VDDIOx IO monitor has been disabled using the MODE bit, the associated system level interrupts (VDDIOxPORRIF and VDDIOxPORFIF) will no longer operate and should be disabled using the respective interrupt enable bit (VDDIOxPORRIE and VDDIOxPORFIE).
Name: VDDIOxCON
Offset: 0x010D

Bit 76543210 
 IOMONLVDEN HYSLVD[3:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 7 – IOMON VDDIOx I/O Monitor Disable(2)

ValueDescription
1 VDDIOx internal voltage monitor and POR circuitry are disabled
0 VDDIOx internal voltage monitor and POR circuitry are enabled

Bit 6 – LVDEN VDDIOx Low Voltage Detect Enable

ValueDescription
1 VDDIOx Low Voltage detect is enabled
0 VDDIOx Low Voltage detect is disabled

Bit 4 – HYS Hysteresis Disable for VDDIOx Low-Voltage Detect(1)

ValueDescription
1 Hysteresis disabled for VDDIOx LVD Trip Point Circuitry
0 Hysteresis enabled for VDDIOx LVD Trip Point Circuitry

Bits 3:0 – LVD[3:0] VDDIOx Low-Voltage Detect Interrupt Trip Point Selection

Refer to the "MVIO Low-Voltage Detect Characteristic” table in the “Electrical Specification” chapter for more details about the voltage detection limit selection.
Reset States: 
POR/BOR = 0000
All other Resets = uuuu
Refer to the MVIO VDDIOx Low-Voltage Detect parameters in the "Electrical Specifications" chapter for more information. When the VDDIOx IO monitor has been disabled using the MODE bit, the associated system level interrupts (VDDIOxPORRIF and VDDIOxPORFIF) will no longer operate and should be disabled using the respective interrupt enable bit (VDDIOxPORRIE and VDDIOxPORFIE).