3.1 MCC Configuration

  • Clock Control configuration:
    • Clock Source: HFINTOSC
    • HF Internal Clock: 64 MHz
    • ADCRC Oscillator: Enabled

Figure 3-1. MCC Clock Control Configuration
  • ADC configuration:
    • Input Configuration: Single-Ended mode
    • Result Format: Right justified
    • VDD: 3.3V
    • Clock Selection: ADCRC

Figure 3-2. MCC ADC Easy View Configuration
  • ADC Context 1 tab:
    • Positive Channel Selection: ANA1
    • Positive Voltage Reference: VDD
    • Operating Mode Selection: Average mode
    • Error Calculation mode: First derivative of single measurement

Figure 3-3. MCC ADC Context 1 Configuration
  • ADC Context 2 tab:
    • Positive Channel Selection: ANA2
    • Positive Voltage Reference: VDD
    • Operating Mode Selection: Basic mode
    • Error Calculation mode: First derivative of single measurement

Figure 3-4. MCC ADC Context 2 Configuration
  • UART2:
    • 115200 baud rate
    • Eight data bits
    • No parity bit
    • One stop bit

Figure 3-5. MCC UART Configuration
  • Pins configuration

Figure 3-6. MCC Pins Configuration

Note: For this example, configure the following settings on the terminal software: Baud rate = 115200, 8-bit data size, one stop bit, no parity bit.