The timer can be configured for a simple hardware-triggered timeout
operation as per the settings shown in Table 2-3.
Table 2-3. Timer Configuration
Timer Setting
Value
START
Rising ERS Edge
RESET
At PR Match
STOP
At PR Match
CSYNC (Clock Sync)
Sync
EPOL (ERS Polarity)
True Level (to start at rising ERS edge)
Inverted Level (to start at falling ERS edge)
PR (Period Register)
Desired Period Value - 1 (e.g., for a desired period
of 20, PR = 19)
The counter starts counting when a rising ERS edge is detected, and counts
until a PR match happens, then rolls over to zero and stops. At PR match, the PRIF
interrupt and output pulse occur, indicating the timeout. The next rising ERS edge will
restart the time delay. This is shown in Figure 2-4. To start the time delay at falling ERS edge, set the
EPOL bit to invert ERS polarity. One-Shot mode can be enabled by setting the OSEN bit to
add a layer of software control, if needed.Figure 2-4. Hardware Triggered Time
Delay
