The timer can be configured for a simple software-triggered timeout
operation as per the settings shown in Table 2-2.
Table 2-2. Timer Configuration
Timer Setting
Value
START
None (ON = 1)
RESET
At PR Match
STOP
At PR Match
CSYNC (Clock Sync)
Sync
OSEN (One-shot)
Enabled
PR (Period Register)
Desired Period Value - 1 (e.g., for a desired period
of 20, PR = 19)
The counter counts until a PR match occurs, and then rolls over to zero and
stops. The ON bit is cleared by one-shot operation. At PR match, the PRIF interrupt and
output pulse occur, indicating the timeout. The software can set the ON bit again to
start another time delay. This is shown in Figure 2-3.Figure 2-3. Software Triggered Time
Delay
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